ADPD4200 datasheet(23/93 Pages) AD

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Data Sheet

ADPD4200

THEORY OF OPERATION

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Rev. 0 | 23 of 93

Table 15. FIFO Status Byte Order and Contents

Byte Order

Enable Bit

Contents1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ENA_STAT_SUM

Any LEV1_x Any LEV0_x

4-bit sequence

ENA_STAT_D1

DATA_H

DATA_G

DATA_F

DATA_E

DATA_D

DATA_C

DATA_B

DATA_A

ENA_STAT_D2

DATA_L

DATA_K

DATA_J

DATA_I

ENA_STAT_L0

LEV0_H

LEV0_G

LEV0_F

LEV0_E

LEV0_D

LEV0_C

LEV0_B

LEV0_A

ENA_STAT_L1

LEV1_H

LEV1_G

LEV1_F

LEV1_E

LEV1_D

LEV1_C

LEV1_B

LEV1_A

ENA_STAT_LX

LEV1_L

LEV1_K

LEV1_J

LEV1_I

LEV0_L

LEV0_K

LEV0_J

LEV0_I

1 DATA_x refers to the data register interrupts for the corresponding time slot. LEV0_x and LEV1_x refer to Level 0 and Level 1 time slot interrupts, respectively, for Time Slot

A through Time Slot L.

Interrupt Outputs, Interrupt X and Interrupt Y

The ADPD4200 supports two separate interrupt outputs, Interrupt X

and Interrupt Y. Each interrupt has the option to be driven to any

of the two GPIOx pins. The two different interrupt outputs can be

generated for a host processor if desired. For example, the FIFO

threshold interrupt, INT_FIFO_TH, can be routed to Interrupt X and

used to drive the direct memory access (DMA) channel of the host,

while the INT_FIFO_ OFLOW and INT_FIFO_UFLOW interrupts

can be routed to Interrupt Y and used to drive an additional host

interrupt pin. Another example case includes routing the data inter-

rupt from a single time slot to Interrupt X and the FIFO threshold

interrupt to Interrupt Y. The host receives one interrupt when the

interrupt of that particular channel occurs and the host can then

read that register directly. Interrupt Y, in this case, is handled by

the host with the DMA or with an interrupt. Each of the different

interrupt status bits can be routed to Interrupt X or Interrupt Y, or

both.

For each interrupt, there is an associated Interrupt X and Interrupt Y

enable bit. The logic for the Interrupt X and Interrupt Y function is a

logic AND of the status bit with its matching enable bit. All enabled

status bits are then logically OR’ed to create the interrupt function.

The enable bits do not affect the status bits.

General-Purpose Inputs and Outputs

The ADPD4200 provides two general-purpose input and output

pins: GPIO0 and GPIO1. These GPIOx pins can be used as previ-

ously described in the Interrupt Outputs, Interrupt X and Interrupt Y

section for interrupt outputs or for providing external clock signals

to the device. The GPIOx pins can also be used for many different

control signals, as synchronization controls to external devices, as

well as test signals that are useful during system debugging. All of

the available signals that can be brought out on a GPIOx pin.

SPI

The ADPD4200 contains a SPI port, which operates synchronously

with its respective input clocks and requires no internal clocks to

operate.

The ADPD4200 has an internal power-on reset circuit that sets the

device into a known idle state during the initial power-up. After the

power-on reset is released, approximately 2 µs to 6 μs after the

DVDD supply is active, the device can be read and written through

the SPI.

The registers are accessed using addresses within a 15-bit address

space. Each address references a 15-bit register with one address

reserved for the FIFO read accesses. Reads and writes auto-incre-

ment to the next register if additional words are accessed as part

of the same access sequence. This automatic address increment

occurs for all addresses except the FIFO address, one less than the

FIFO address and the last used address, which is 0x277. Reads

from the FIFO address continue to access the next byte from the

FIFO.

SPI Operations

The SPI single register write operation is shown in Figure 22. The

first two bytes contain the 15-bit register address and specify that a

write is requested. The remaining two bytes are the 16 data bits to

write to the register. The register write occurs only when all 16 bits

are shifted in prior to deassertion of the CS signal.

In addition, multiple registers can be written if an additional 16-bit

data is shifted in before deassertion of the CS signal. The register

address automatically increments to the next register after each

16 bits of data.

The SPI single register read operation is shown in Figure 23. The

first two bytes contain the 15-bit register address and specify that

a read is requested. Register bits are shifted out starting with the

MSB. In addition, multiple registers can be read if an additional

16-bit data is shifted out prior to deassertion of the CS signal.

It is recommended that reading from the FIFO is performed byte

wise. There is no requirement to read multiples of 16 bits.

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