ADPD4200 datasheet(22/93 Pages) AD

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Data Sheet

ADPD4200

THEORY OF OPERATION

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Rev. 0 | 22 of 93

EXECUTION MODES

A state machine in the low frequency oscillator clock domain

controls sleep times, wake-up cycles, and the start of time slot

operations. The low frequency oscillator serves as the time base

for all time slot operations, controls the sample rates, and clocks

the low frequency state machine. This state machine controls all

operations and is controlled by the OP_MODE bit.

Table 14. OP_MODE Bit Setting Descriptions

OP_MODE Setting

Mode

Description

Standby

All operations stopped. Time slot ac-

tions reset. Low power standby state.

Transitioning to this state from standby

mode starts time slot operation.

At power-up and following any subsequent reset operations, the

ADPD4200 is in standby mode. The user can write 0 to the

OP_MODE bit to immediately stop operations and return to standby

mode.

go mode. The user must enter standby mode before changing the

control registers. Standby mode resets the digital portion of the

ADC, all of the pulse generators, and the state machine.

When OP_MODE is set to 1, the device immediately starts the first

wake-up sequence and time slot operations unless using an exter-

nal synchronization trigger. If using an external synchronization

trigger, the device enters the sleep state before the first wake-up

and time slot regions begin.

HOST INTERFACE

The ADPD4200 provides a SPI to communicate with the host.

The device also provides numerous FIFO, data register, error, and

threshold status bits, each of which can be provided by an interrupt

function from a GPIOx, read from status registers, or appended as

optional status bytes at the end of a FIFO packet.

Interrupt Status Bits

Data Register Interrupts

The data interrupt status bits, INT_DATA_x for each time slot, are

set every time that the data registers for each time slot are updated.

The state of the HOLD_REGS_x bit has no effect on the interrupt

logic.

FIFO Threshold Interrupt

The FIFO threshold interrupt status bit, INT_FIFO_TH, is set when

the number of bytes in the FIFO exceeds the value stored in the

FIFO_TH register. The INT_FIFO_TH bit is cleared automatically

when a FIFO read reduces the number of bytes below the value in

the FIFO_TH register, which allows the user to set an appropriate

data size for their host needs.

Level Interrupts

Two level interrupt status bits, INT_LEV0_x and INT_LEV1_x, pro-

vide an interrupt when the dark data or signal data values cross

greater than or less than a programmed threshold level.

Two comparison circuits are available per time slot. The

INT_LEV0_x or INT_LEV1_x status bits are set when the da-

ta register update meets the criteria set by the associated

THRESH0_TYPE_x, THRESH0_DIR_x, THRESH0_CHAN_x set-

tings, or by the associated THRESH1_TYPE_x, THRESH1_DIR_x,

and THRESH1_CHAN_x settings.

The Level 0 interrupt operates as follows. The user sets an

8-bit threshold value in the THRESH0_VALUE_x bit field for the

corresponding time slot. This value is then shifted to the left

by anywhere from 0 bits to 24 bits, specified by the setting of

the THRESH0_SHIFT_x bit field. A comparison is then made be-

tween the shifted threshold value and the register chosen by the

THRESH0_TYPE_x bit field and the THRESH0_CHAN_x bit. The

INT_LEV0_x status bit is set if the selected data register meets the

criteria set in the THRESH0_DIR_x bit field. The Level 1 interrupt

operates in the same fashion.

Clearing Interrupt Status Bits

All status bits are set regardless of whether the status bit is routed

to one of the interrupt outputs, Interrupt X or Interrupt Y. The status

bits are independent of the interrupt enable bits. The status bits are

always set by the corresponding event. The interrupt bits stay set

until they are either manually or automatically cleared.

The user can manually clear a given interrupt by writing a 1 to

the matching interrupt status bit. In addition, the data interrupt

status bits can be configured to clear automatically. When the

INT_ACLEAR_DATA_x or INT_ACLEAR_FIFO bit is set, the appro-

priate interrupt status bit is automatically cleared when any match-

ing data register or FIFO register is read. Automatic clearing of

the interrupt status bits removes the need to manually clear these

interrupts.

Optional Status Bytes

There is an option to append each data packet with status bits. This

option is useful for hosts that cannot spare an interrupt channel

to service. The status bytes can each be individually selected

in the FIFO_STATUS_BYTES register. Each bit in the FIFO_ STA-

TUS_BYTES register enables a status byte that is appended to the

data packet in the FIFO. If any bit in the FIFO_STATUS_ BYTES

contains the status bits, as shown in Table 15. Table 15 shows the

order, enable bit, and contents of each status byte.

The 4-bit sequence number cycles from 0 to 15 and is incremented

with a wraparound every time the time slot sequence completes.

This sequence number can also be made available bitwise on the

GPIOx pins.

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