ADPD4200 datasheet(71/93 Pages) AD

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Data Sheet

ADPD4200

analog.com

Rev. 0 | 71 of 93

INTERRUPT STATUS AND CONTROL REGISTERS

Table 27. Interrupt Status and Control Register Details

Addr

Name

Bits

Bit Name

Description

Reset Access1

0x0000

FIFO_STATUS

CLEAR_FIFO

Clear FIFO. Write a 1 to empty the FIFO while the FIFO is not

being accessed, which resets FIFO_BYTE_COUNT and clears the

INT_FIFO_OFLOW, INT_FIFO_UFLOW, and INT_FIFO_TH status

bits.

0x0

R/W1C

INT_FIFO_UFLOW

FIFO Underflow Error. This bit is set when the FIFO is read while

empty. Write 1 to this bit to clear the interrupt. This bit is also cleared

if the FIFO is cleared using the CLEAR_FIFO bit.

0x0

R/W1C

INT_FIFO_OFLOW

FIFO Overflow Error. This bit is set when data was not written to the

FIFO due to lack of space. Write 1 to this bit to clear the interrupt.

This bit is also cleared if the FIFO is cleared with the CLEAR_FIFO

bit.

0x0

R/W1C

[12:11]

Reserved

Reserved.

0x0

[10:0]

FIFO_BYTE_COUNT

This field indicates the number of bytes in the FIFO.

0x0

0x0001

INT_STATUS_DATA

INT_FIFO_TH

FIFO_TH Interrupt Status. This bit is set during a FIFO write when

the number of bytes in the FIFO exceeds the FIFO_TH register

value. Write 1 to this bit to clear this interrupt. This bit can also be

automatically cleared when the FIFO_DATA register is read if the

INT_ACLEAR_FIFO bit is set.

0x0

R/W1C

[14:12]

Reserved

Reserved.

0x0

INT_DATA_L

Time Slot L Data Register Interrupt Status. This bit is set every time

the Time Slot L data registers are updated. Write 1 to this bit to clear

the interrupt. The interrupt is cleared automatically when the Time

Slot L data registers are read if the INT_ACLEAR_DATA_L bit is set.

0x0

R/W1C

INT_DATA_K

Time Slot K Data Register Interrupt Status. This bit is set every time

the Time Slot K data registers get updated. Write 1 to this bit to clear

the interrupt. The interrupt is cleared automatically when the Time

Slot K data registers are read if the INT_ACLEAR_DATA_K bit is set.

0x0

R/W1C

INT_DATA_J

Time Slot J Data Register Interrupt Status. This bit is set every time

the Time Slot J data registers are updated. Write 1 to this bit to clear

the interrupt. The interrupt is cleared automatically when the Time

Slot J data registers are read if the INT_ACLEAR_DATA_J bit is set.

0x0

R/W1C

INT_DATA_I

Time Slot I Data Register Interrupt Status. This bit is set every time

the Time Slot I data registers are updated. Write 1 to this bit to clear

the interrupt. The interrupt is cleared automatically when the Time

Slot I data registers are read if the INT_ACLEAR_DATA_I bit is set.

0x0

R/W1C

INT_DATA_H

Time Slot H Data Register Interrupt Status. This bit is set every time

the Time Slot H data registers are updated. Write 1 to this bit to clear

the interrupt. The interrupt is cleared automatically when the Time

Slot H data registers are read if the INT_ACLEAR_DATA_H bit is set.

0x0

R/W1C

INT_DATA_G

Time Slot G Data Register Interrupt Status. This bit is set every time

the Time Slot G data registers are updated. Write 1 to this bit to clear

the interrupt. The interrupt is cleared automatically when the Time

Slot G data registers are read if the INT_ACLEAR_DATA_G bit is

set.

0x0

R/W1C

INT_DATA_F

Time Slot F Data Register Interrupt Status. This bit is set every time

the Time Slot F data registers are updated. Write 1 to this bit to clear

the interrupt. The interrupt is cleared automatically when the Time

Slot F data registers are read if the INT_ACLEAR_DATA_F bit is set.

0x0

R/W1C

INT_DATA_E

Time Slot E Data Register Interrupt Status. This bit is set every time

the Time Slot E data registers are updated. Write 1 to this bit to clear

the interrupt. The interrupt is cleared automatically when the Time

Slot E data registers are read if the INT_ACLEAR_DATA_E bit is set.

0x0

R/W1C

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