ADPD4200 datasheet(19/93 Pages) AD

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Data Sheet

ADPD4200

THEORY OF OPERATION

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Rev. 0 | 19 of 93

The FIFO is never written with partial packets of data. If there

is not enough room for all of the data to be written to the FIFO

for all enabled time slots and any selected status bytes, no data

is written from any of the time slots during that period, and the

INT_FIFO_OFLOW status bit is set.

The order of samples written to the FIFO (if selected) is dark data

followed by signal data. The byte order for multibyte words is shown

in Table 13.

Table 13. Byte Order for FIFO Writes

Size

Byte Order (After Shift)

[7:0]

[15:8], [7:0]

[15:8], [7:0], [23:16]

[15:8], [7:0], [31:24], [23:16]

The FIFO size is 512 bytes. When the FIFO is empty, a read

operation returns 0xFF, and the INT_FIFO_UFLOW status bit is set.

In addition to the FIFO, the signal and dark 32-bit registers can

be directly read. These registers are effectively two-stage registers

where there is an internal data register that updates with every

sample and a latched output data register that is accessed by the

host. The data interrupts can be used to align the access of these

registers to just after the registers are written. If using the interrupt

timing is troublesome, use the HOLD_REGS_x bit field to prevent

update of the output registers during access not aligned to the

interrupt. Setting the HOLD_REGS_x bit field blocks the update

of the latched output data register and ensures that the dark and

signal values read by the host are from the same sample point. If

additional samples occur while the HOLD_REGS_x bit field is set,

the samples are written to the internal data register but not latched

into the output data register that is accessed by the host. Setting

the HOLD_REGS_x bit field to 0 reenables the pass through of new

data.

After all time slots have completed, the optional status bytes are

written to the FIFO. See the Optional Status Bytes section for more

information.

CLOCKING

Low Frequency Oscillator

A low frequency oscillator clocks the low speed state machine,

which sets the time base used to control the sample timing,

wake-up states, and overall operation. There are three options for

low frequency oscillator generation. The first option is an internal,

selectable 32 kHz or 1 MHz oscillator. The second option is for the

host to provide a low frequency oscillator externally. Finally, the low

frequency oscillator can be generated by a divide by 32 or divide

by 1000 of an external high frequency clock source at 32 MHz.

When powering up the device, it is expected that the low frequency

oscillator is enabled and left running continuously.

To operate with the on-chip low frequency oscillator, use the follow-

ing writes. Set the LFOSC_SEL bit to 0 to select the 32 kHz

clock or 1 if the 1 MHz clock is desired. Then, set either the

OSC_1M_EN or OSC_32K_EN bit to 1 to turn on the desired

internal oscillator. The internal 32 kHz clock frequency is set using

the 6-bit OSC_32K_ADJUST bit field. The internal 1 MHz clock

frequency is set using the 10-bit OSC_1M_FREQ_ ADJ bit field.

If higher timing precision is required than can be provided by the

on-chip low frequency oscillator, this oscillator can be driven directly

from an external source provided on a GPIOx input. To enable an

external low frequency clock, use the following writes. Enable one

of the GPIOx inputs using the GPIO_PIN_CFGx bit fields. Next,

use the ALT_CLK_GPIO bit field to choose the enabled GPIOx

input to be used for the external low frequency oscillator. Set the

ALT_CLOCKS bit field to 0x1 to select an external low frequency

oscillator. Finally, use the LFOSC_SEL bit to match whether a

32 kHz or 1 MHz clock is being provided.

In a third method, an external 32 MHz clock is used for both the

high frequency clock and to be divided down to generate the low

frequency clock. To use this method, follow the previous instruc-

tions for an external low frequency clock but set the ALT_CLOCKS

bit field to 0x3, and use the LFOSC_SEL bit to determine if a divide

by 32 or 1000 is used to generate the low frequency clock so that

either a 32 kHz or 1 MHz clock is generated from the external

32 MHz clock.

High Frequency Oscillator

A 32 MHz high frequency oscillator is generated internally or can

be provided externally. This high frequency clock clocks the high

speed state machine, which controls the AFE operations during the

time slots, such as LED timing and integration times.

The high frequency oscillator can be internally generated by setting

the ALT_CLOCKS bits to 0x0 or 0x1. When selected, the internal

32 MHz oscillator is enabled automatically by the low speed state

machine during the appropriate wake-up time or during the 32 MHz

oscillator calibration routine.

The high frequency oscillator can also be driven from an external

source. To provide an external 32 MHz high frequency oscillator,

enable one of the GPIOx inputs using the GPIO_PIN_CFGx bits.

Then, use the ALT_CLK_GPIO bits to choose the enabled GPIOx

input for the external high frequency oscillator. Finally, write 0x2 or

0x3 to the ALT_CLOCKS bits to select an external high frequency

oscillator. Writing 0x2 provides only the high frequency oscillator

from the external source, whereas writing 0x3 generates both the

low frequency oscillator and high frequency oscillator from the

external 32 MHz source. When using an external 32 MHz oscillator,

it must be kept running continuously for proper device operation.

TIME STAMP OPERATION

The time stamp feature is useful for calibration of the low frequency

oscillator as well as providing the host with timing information

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