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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADFS5758 датащи(PDF) 11 Page - Analog Devices |
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ADFS5758 датащи(HTML) 11 Page - Analog Devices |
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11 / 75 page  Data Sheet ADFS5758 Rev. 0 | Page 11 of 75 TIMING CHARACTERISTICS AVDD1 = VDPC+ = 15 V; dc-to-dc converter disabled; AVDD2 = 5 V; AVSS = −15 V; VLOGIC = 1.71 V to 5.5 V; AGND = DGND = REFGND = PGND1 = 0 V; REFIN = 2.5 V external; voltage output: RL = 1 kΩ, CL = 220 pF; current output: RL = 300 Ω; all specifications at TA = −40°C to +105°C, TJ < 125°C, unless otherwise noted. Table 3. Parameter1, 2, 3 1.71 V ≤ VLOGIC < 3 V 3 V ≤ VLOGIC ≤ 5.5 V Unit Description t1 33 20 ns min SCLK cycle time, write operation 120 66 ns min SCLK cycle time, read operation t2 16 10 ns min SCLK high time, write operation 60 33 ns min SCLK high time, read operation t3 16 10 ns min SCLK low time, write operation 60 33 ns min SCLK low time, read operation t4 10 10 ns min SYNC falling edge to SCLK falling edge setup time, write operation 33 33 ns min SYNC falling edge to SCLK falling edge setup time, read operation t5 10 10 ns min 24th/32nd SCLK falling edge to SYNC rising edge t6 500 500 ns min SYNC high time (all register writes outside of those listed in this table) 1.5 1.5 μs min SYNC high time (DAC_INPUT register write) 500 500 μs min SYNC high time (DAC_CONFIG register write, where the range bits, Bits[3:0], change; see the Calibration Memory CRC section) t7 5 5 ns min Data setup time t8 6 6 ns min Data hold time t9 750 750 ns min LDAC falling edge to SYNC rising edge t10 1.5 1.5 μs min SYNC rising edge to LDAC falling edge t11 250 250 ns min LDAC pulse width low t12 600 600 ns max LDAC falling edge to DAC output response time, digital slew rate control disabled 2 2 μs max LDAC falling edge to DAC output response time, digital slew rate control enabled t13 See the AC Performance Characteristics section μs max DAC output settling time t14 1.5 1.5 μs max SYNC rising edge to DAC output response time (LDAC = 0) t15 5 5 μs min RESET pulse width t16 40 28 ns max SCLK rising edge to SDO valid t17 100 100 μs min RESET rising edge to first SCLK falling edge after SYNC falling edge (t17 does not appear in the timing diagrams) 1 Guaranteed by design and characterization. Not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of VLOGIC) and timed from a voltage level of 1.2 V. tR is rise time. tF is fall time. 3 See Figure 2 to Figure 5. |
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