ADFS5758 datasheet(63/75 Pages) AD

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Data Sheet

ADFS5758

Rev. 0 | Page 63 of 75

DC-to-DC Configuration 1 Register

Address: 0x0B, Reset: 0x0B0000, Name: DCDC_CONFIG1

This register is used to configure the dc-to-dc controller mode.

Table 39. Bit Descriptions for DCDC_CONFIG1

Bits

Bit Name

Description

Reset

Access

FAULT_PIN_STATUS

The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.

0x0

[20:16]

REGISTER_ADDRESS

0x0

[15:8]

Reserved

Reserved. Do not alter the default value of these bits.

0x0

Reserved

Reserved. Do not alter the default value of this bit.

0x0

R/W

[6:5]

DCDC_MODE

These two bits configure the dc-to-dc converters.

0x0

R/W

00: DC-to-DC converter powered off (default).

01: DPC current mode. The positive DPC rail tracks the headroom of the current

output buffer.

10: DPC voltage mode. The positive DPC rail is regulated to 15 V with respect to

−VSENSE.

11: PPC current mode. VDPC+ is regulated to a user programmable level between 5 V

and 25.677 V (depending on the DCDC_VPROG bits, Bits[4:0]) with respect to −VSENSE.

The ENABLE_PPC_BUFFERS bit (Bit 11 in the ADC_CONFIG register) must be set prior

to enabling PPC current mode.

[4:0]

DCDC_VPROG

DC-to-dc programmed voltage in PPC mode. VDPC+ is regulated to a user programmable

level between 5 V (0b00000) and 25.677 V (0b11111), in steps of 0.667 V. VDPC+ is

regulated with respect to −VSENSE.

0x0

R/W

DC-to-DC Configuration 2 Register

Address: 0x0C, Reset: 0x0C0100, Name: DCDC_CONFIG2

This register configures various dc-to-dc die features, such as the dc-to-dc converter current limit and the dc-to-dc die node, to be

multiplexed to the ADC.

Table 40. Bit Descriptions for DCDC_CONFIG2

Bits

Bit Name

Description

Reset

Access

FAULT_PIN_STATUS

The FAULT_PIN_STATUS bit reflects the inverted current status of the

FAULT pin.

0x0

[20:16]

REGISTER_ADDRESS

0x0

[15:13]

Reserved

Reserved. Do not alter the default value of these bits.

0x0

BUSY_3WI

Three-wire interface busy indicator.

0x0

0: 3-wire interface not currently active.

1: 3-wire interface busy.

INTR_SAT_3WI

Three-wire interface saturation flag. This flag is set to 1 when the

interrupt detection circuitry is automatically disabled due to six

consecutive interrupt signals. A write to either of the dc-to-dc

configuration registers clears this bit to 0.

0x0

DCDC_READ_COMP_DIS

Disable 3-wire interface read and compare cycle. This read and compare

cycle ensures that the contents of the copy of the dc-to-dc configuration

registers on the main die match the contents on the dc-to-dc die.

0x0

R/W

0: enable automatic read and compare cycle (default).

1: when set, this bit disables the automatic read and compare cycle

after each 3-wire interface write.

[9:8]

Reserved

Reserved. Do not alter the default value of these bits.

0x1

R/W

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