ADFS5758 datasheet(46/75 Pages) AD

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ADFS5758

Data Sheet

Rev. 0 | Page 46 of 75

ADFS5758

AVSS

AGND

AVDD2

DGND

SCLK

SDI

SDO

SYNC

FAULT

DATA AND

CONTROL

REGISTERS

DIGITAL

BLOCK

WATCHDOG

TIMER

STATUS

POWER-ON

RESET

REFERENCE

BUFFERS

DAC

REG

VREF

CALIBRATION

MEMORY

VOUT

RANGE

SCALING

REFOUT

REFIN

AD1

AD0

16-BIT

DAC

SW+

VDPC+

USER GAIN

USER OFFSET

+VSENSE

–VSENSE

CHART

IOUT

RANGE

SCALING

IOUT

VOUT

DC-TO-DC DIE

CLKOUT

REFGND

NOTES

1. GRAY ITEMS REPRESENT DIAGNOSTIC ADC INPUT NODES.

VLOGIC

VIOUT

CCOMP

PGND1

TEMPERATURE

SENSOR

ANALOG

DIAGNOSTICS

INDEPENDENT

MONITORING

ADC

RESET

VLDO

VDPC+

MCLK

10MHz

RSET

LDAC

HART_EN

3-WIRE INTERFACE

TEMPERATURE,

INTERNAL 2.5V SUPPLY,

DC-TO-DC DIE TO AGND

–VSENSE BUFFER

+VSENSE BUFFER

REFIN BUFFER

REFOUT

POWER MANAGEMENT

BLOCK

INT_AVCC, REF2

AVDD1

–

ADC1

ADC2

Figure 86. Diagnostic ADC Input Nodes

ADC Accuracy Calculations

The ADC accuracy is dependent on the input node being

converted.

If the ADC1 pin is used to monitor the IOUT return current (see

Figure 85), the overall ADC conversion accuracy can be

calculated by summing the following components:

•

ADC accuracy for the ADC1 pin input node.

•

Accuracy of external RSENSE resistor.

•

TC of the external RSENSE resistor.

ADC Configuration

The ADC is configured using the ADC_CONFIG register via

the SEQUENCE_COMMAND (Bits[10:8]), the SEQUENCE_

DATA (Bits[7:5]), and the ADC_IP_SELECT[4:0] bits.

Table 20. ADC Configuration Register

[D10:D8]

[D7:D5]

[D4:D0]

Command

Data

ADC input select

The ADC can be set up to monitor a single node of interest or

configured to sequence through up to eight nodes of interest.

The sequential conversions can be initiated automatically after

each valid SPI frame is received by the device (automatic sequence

mode), or in a more controlled manner via a specific key

code written to the key register (key sequence mode). When a

conversion is complete, the ADC result is available in the status

advanced. If autostatus readback mode is used in conjunction with

either sequence mode, the last completed ADC conversion data is

available on SDO during each SPI frame written to the device.

The sequencer has a maximum channel depth of 8. Each of the

channels in the sequencer must be configured with the select

bits of the required ADC input for that sequencer channel, and

the number of configured channels must equal the depth. If any

active sequencer channel location is not configured correctly, it

stores the previous value loaded to that channel, defaulting

initially to the ADC input option of 0b00000 for all sequencer

channels. Note that, if a node from the dc-to-dc die is required

to be part of the ADC sequencer, preconfigure this node using

the DCDC_ADC_CONTROL_DIAG bits in the DCDC_

CONFIG2 register before configuring the ADC sequencer to

avoid any 3WI related delays between ADC conversions. If

multiple nodes from the dc-to-dc die are required within the

sequence, key sequencing mode must be used rather than

automatic sequencing mode, because the DCDC_ADC_

CONTROL_DIAG bits must be updated between ADC

conversions to configure the next required dc-to-dc die

node required by the sequence.

The four modes of operation are key sequencing, automatic

sequencing, single immediate conversion, and single-key conver-

sion. The sequencing modes are mutually exclusive. If enabled,

the key sequencing mode disables the automatic sequencing

mode and vice versa.

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