ADFS5758 datasheet(65/75 Pages) AD

65 / 75 page

Data Sheet

ADFS5758

Rev. 0 | Page 65 of 75

Bits

Bit Name

Description

Reset

Access

[5:4]

WINDOW_WIDTH

Configure WDT window width. The watchdog timer uses a center threshold and a

window width, where the width is a fraction of the center threshold. If the window

width is set to 1/1 (default), the watchdog timer is monitored for late watchdog

timer resets only. If, however, the window width is set to any value other than 1/1,

the watchdog timer is monitored for early or late reset events.

0x0

R/W

00: 1/1 (default).

01: 1/2.

10: 1/4.

11: 1/8.

[3:0]

CENTER_THRESHOLD

Set the center of the window threshold timeout. Setting CENTER_THRESHOLD[3:0]

to a binary value beyond 0b1010 results in the default setting of 1 second

0x9

R/W

0000: 1 ms.

0001: 5 ms.

0010: 10 ms.

0011: 25 ms.

0100: 50 ms.

0101: 100 ms.

0110: 250 ms.

0111: 500 ms.

1000: 750 ms.

1001: 1 sec (default).

1010: 2 sec.

Digital Diagnostic Configuration Register

Address: 0x10, Reset: 0x10005D, Name: DIGITAL_DIAG_CONFIG

This register configures various digital diagnostic features of interest for a particular application.

Table 42. Bit Descriptions for DIGITAL_DIAG_CONFIG

Bits

Bit Name

Description

Reset

Access

FAULT_PIN_STATUS

The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.

0x0

[20:16]

REGISTER_ADDRESS

0x0

[15:9]

RESERVED

Reserved.

0x0

[8:7]

BKGND_CRC_MON_MODE

Select memory map CRC monitoring mode.

0x0

R/W

00: user controls CRC check using a key code (default).

01: CRC automatically done on completion of any valid SPI frame.

10: CRC runs continually in background.

11: CRC runs continually in background.

DAC_LATCH_MON_EN

Enable a diagnostic monitor on the DAC latches. This feature monitors the actual

digital code driving the DAC and compares it with the digital code generated within

the digital block. Any difference between the two codes causes the

DAC_LATCH_MON_ERR flag to be set in the DIGITAL_DIAG_RESULTS register.

0x1

R/W

0: disable.

1: enable (default).

DUAL_CAL_EN

Enable internal calibration on the 16-bit user DAC code to be completed twice.

The DAC is only updated if both results match. If a fail is registered, no DAC

write occurs and the DUAL_CAL_ERR flag in the DIGITAL_DIAG_RESULTS register is

set. Note that t14 (SYNC rising edge to DAC output response time) extends from

1.5 μs to 2 μs if this feature is enabled.

0x0

R/W

0: disable (default).

1: enable.

ADFS5758 датащи(PDF) 65 Page - Analog Devices

ADFS5758 датащи(HTML) 65 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

датащи скачать

ссылки URL