ADFS5758 datasheet(64/75 Pages) AD

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ADFS5758

Data Sheet

Rev. 0 | Page 64 of 75

Bits

Bit Name

Description

Reset

Access

VIOUT_OV_ERR_DEGLITCH

Adjust the deglitch time on VIOUT overvoltage error flag.

0x0

R/W

0: deglitch time set to 1.02 ms (default).

1: deglitch time set to 128 μs.

VIOUT_PULLDOWN_EN

Enable the 30 kΩ resistor to ground on VIOUT.

0x0

R/W

0: disable (default).

1: enable.

[5:4]

DCDC_ADC_CONTROL_DIAG

Select which dc-to-dc die node is multiplexed to the ADC on the

main die.

0x0

R/W

00: AGND on dc-to-dc die.

01: internal 2.5 V supply on dc-to-dc die.

10: AVDD1.

11: reserved (do not select this option).

[3:1]

DCDC_ILIMIT

These three bits set the dc-to-dc converter current limit.

0x0

R/W

000: 150 mA (default).

001: 200 mA.

010: 250 mA.

011: 300 mA.

100: 350 mA.

101: 400 mA.

110: 400 mA.

111: 400 mA.

Reserved

Reserved.

0x0

R/W

Watchdog Timer (WDT) Configuration Register

Address: 0x0F, Reset: 0x0F0009, Name: WDT_CONFIG

This register configures the WDT timeout values. This register also configures the WDT setup in terms of acceptable resets and the

resulting response to a WDT fault (for example, clear the output or reset the device).

Table 41. Bit Descriptions for WDT_CONFIG

Bits

Bit Name

Description

Reset

Access

FAULT_PIN_STATUS

The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.

0x0

[20:16]

REGISTER_ADDRESS

0x0

[15:11]

RESERVED

Reserved.

0x0

CLEAR_ON_WDT_FAIL

Enable clear on watchdog timer fault. If the watchdog timer times out, a clear event

occurs, whereby the output is loaded with the clear code stored in the

CLEAR_CODE register.

0x0

R/W

0: disable (default).

1: enable.

RESET_ON_WDT_FAIL

Enable a software reset to automatically occur if the WDT times out.

0x0

R/W

0: disable (default).

1: enable.

KICK_ON_VALID_WRITE

Enable any valid SPI command to reset the WDT. Any active WDT error flags must

be cleared before the WDT can be restarted.

0x0

R/W

0: disable (default).

1: enable.

DOUBLE_WR_KICK_EN

When this bit is set, two specific consecutive keys codes are required to kick the

watchdog timer. Note that any active WDT error flags need to be cleared before the

WDT can be restarted.

0x0

R/W

0: disable (default). A single key code is required to kick the watchdog timer.

1: enable. A double key code is required to kick the watchdog timer.

WDT_EN

Enable the WDT. The next kick starts the watchdog, assuming there are no active

WDT fault flags.

0x0

R/W

0: disable (default).

1: enable.

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