ADF4252BCPZ-R7 datasheet(13/30 Pages) AD

13 / 30 page

Data Sheet

ADF4252

Rev. E | Page 13 of 30

THEORY OF OPERATION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 29. SW1 and SW2

are normally closed switches. SW3 is normally open. When

power-down is initiated, SW3 is closed, and SW1 and SW2 are

opened. This ensures that there is no loading of the REFIN pin

on power-down.

POWER-DOWN

CONTROL

REFIN NC

SW3

SW2

SW1

100kΩ

BUFFER

TO R

COUNTER

NC = NORMALLY CLOSED

NO = NORMALLY OPEN

REFOUT

XOEB

Figure 29. Reference Input Stage

RF AND IF INPUT STAGE

The RF input stage is shown in Figure 30. The IF input stage is

the same. It is followed by a two-stage limiting amplifier to

generate the CML clock levels needed for the N counter.

2kΩ

1.6V

BIAS

GENERATOR

RFINA

RFINB

VDD1

AGND

Figure 30. RF Input Stage

RF INT DIVIDER

The RF INT CMOS counter allows a division ratio in the PLL

feedback counter. Division ratios from 31 to 255 are allowed.

INT, FRAC, MOD, AND R RELATIONSHIP

The INT, FRAC, and MOD values, in conjunction with the RF

R counter, make it possible to generate output frequencies that

are spaced by fractions of the RF phase frequency detector (PFD).

The equation for the RF VCO frequency (RFOUT) is



















MOD

FRAC

INT

PFD

OUT

(1)

where:

RFOUT is the output frequency of external VCO.

fPFD is the PFD frequency (see Equation 2).

INT is the preset divide ratio of the binary 8-bit counter (31 to 255).

FRAC is the preset fractional ratio of the binary 12-bit

programmable FRAC counter (0 to MOD).

MOD is the preset modulus ratio of the binary 12-bit

programmable FRAC counter (2 to 4095).

REF

PFD

)

( 





(2)

where:

REFIN is the reference input frequency.

D is the RF REFIN doubler bit.

R is the preset divide ratio of the binary 4-bit programmable

reference counter (1 to 15).

N = INT + FRAC/MOD

FROM RF

INPUT STAGE

TO PFD

RF N DIVIDER

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

MOD

REG

INT

REG

FRAC

VALUE

N-COUNTER

Figure 31. N Counter

RF R COUNTER

The 4-bit RF R counter allows the input reference frequency

(REFIN) to be divided down to produce the reference clock to

the RF PFD. Division ratios from 1 to 15 are allowed.

IF R COUNTER

The 15-bit IF R counter allows the input reference frequency

(REFIN) to be divided down to produce the reference clock to

the IF PFD. Division ratios from 1 to 32,767 are allowed.

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