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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADF4252BCPZ-R7 датащи(PDF) 29 Page - Analog Devices |
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ADF4252BCPZ-R7 датащи(HTML) 29 Page - Analog Devices |
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29 / 30 page  Data Sheet ADF4252 Rev. E | Page 29 of 30 PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE The leads on the chip scale package (CP-24-10) are rectangular. The printed circuit board pad for these must be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land must be centered on the pad. This ensures that the solder joint size is maximized. The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board must be at least as large as this exposed pad. On the printed circuit board, there must be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. This ensures that shorting is avoided. Thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they must be incorporated in the thermal pad at 1.2 mm pitch grid. The via diameter must be between 0.3 mm and 0.33 mm, and the via barrel must be plated with 1 oz copper to plug the via. The user must connect the printed circuit board to AGND. IFOUT J6 C15 100pF R12 18Ω R13 18Ω C16 100pF VCO2 RFOUT VCC VIN 10 14 2 C4 10pF 6.3V R48 0Ω R44 0Ω VVCO R17 13kΩ C20 82pF C19 2.2nF C18 270pF R16 7.5kΩ R15 51Ω C17 100pF R14 18Ω C10 10pF C9 22µF C3 22µF 6.3V VP C6 10pF C5 22µF 6.3V C8 10pF C7 22µF 6.3V VP2 CPIF IFINA R43 0Ω R1 20Ω VDD’ VDD RFOUT J7 C27 100pF R22 18Ω R21 18Ω C26 100pF VCO1 RFOUT VCC VIN 10 14 2 C30 10pF C29 22µF 6.3V R49 0Ω VVCO R20 470Ω C25 3.3nF C24 100nF C23 10nF R19 270Ω R24 51Ω C28 100pF R23 18Ω C12 10pF C11 22µF 6.3V VP VP1 CPRF RFINA C44 100pF CPGND1 RFINB AGND1 DGND AGND2 CPGND2 MUXOUT R27 10kΩ T16 R28 10kΩ R29 10kΩ D4 VDD CLK C43 100pF R27 2.7kΩ DATA LE T14 R39 0Ω R26 1kΩ R4 1MΩ R11 51Ω Y2 10MHz C31 33pF C32 33pF C14 1nF C13 1nF REFIN J5 T13 R47 0Ω Y3 B+ O/P 4 3 2 GND C45 10pF C46 22µF R46 0Ω R45 0Ω 3V 5V U1 ADF4252BCP REFOUT J8 R38 0Ω U6 1 2 4 VCC R35 0Ω R34 0Ω 5V 3V VCO190–540T VCO190–1730T Figure 44. Typical PLL Circuit Schematic |
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