ADF4252BCPZ-R7 datasheet(27/30 Pages) AD

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Data Sheet

ADF4252

Rev. E | Page 27 of 30

One possible setup is feeding the 13 MHz directly to the PFD

and programming the modulus to divide by 65. This results in

the required 200 kHz resolution.

Another possible setup is using the reference doubler to create

26 MHz from the 13 MHz input signal. This 26 MHz is then fed

into the PFD. The modulus is now programmed to divide by 130,

which also results in 200 kHz resolution. This offers superior

phase noise performance over the previous setup.

The programmable modulus is also very useful for multistandard

applications. If a dual-mode phone requires PDC and GSM1800

standards, the programmable modulus is a huge benefit. PDC

requires 25 kHz channel step resolution, whereas GSM1800

requires 200 kHz channel step resolution. A 13 MHz reference

signal can be fed directly to the PFD. The modulus is then

programmed to 520 when in PDC mode (13 MHz/520 = 25 kHz).

The modulus would be reprogrammed to 65 for GSM1800

operation (13 MHz/65 = 200 kHz). It is important that the PFD

frequency remains constant (13 MHz). This allows the user to

design one loop filter that can be used in both setups without

any stability issues. It is the ratio of the RF frequency to the PFD

frequency that affects the loop design. Keeping this relationship

constant, and instead changing the modulus factor, results in a

stable filter.

SPURIOUS OPTIMIZATION AND FASTLOCK

As mentioned in the Noise and Spur Setting section, the device

can be optimized for spurious performance. However, in fast

locking applications, the loop bandwidth needs to be wide.

Therefore, the filter does not provide much attenuation of the

spurious outputs. The programmable charge pump can be used

to avoid this issue. The filter is designed for a narrow-loop

bandwidth so that steady-state spurious specifications are met.

This is designed using the lowest charge pump current setting.

To implement fast lock during a frequency jump, the charge

pump current is set to the maximum setting for the duration of

the jump. This has the effect of widening the loop bandwidth,

which improves lock time. When the PLL has locked to the new

frequency, the charge pump is again programmed to the lowest

charge pump current setting. This narrows the loop bandwidth

to its original cutoff frequency to allow better attenuation of the

spurious outputs than the wide-loop bandwidth.

SPURIOUS SIGNALS—PREDICTING WHERE THEY

APPEAR

Just as in integer-N PLLs, spurs appear at PFD frequency offsets

on either side of the carrier (and multiples of the PFD frequency).

In a fractional-N PLL, spurs also appear at frequencies equal to

the RFOUT channel step resolution (fRES). The ADF4252 uses a

high-order fractional interpolator engine, which results in spurs

also appearing at frequencies equal to half of the channel step

resolution. For example, examine the GSM1800 setup with a

26 MHz PFD and 200 kHz resolution. Spurs appear at ±26 MHz

from the RF carrier (at an extremely low level due to filtering).

Also, there are spurs at ±200 kHz from the RF carrier. Due to

the fractional interpolator architecture used in the ADF4252,

spurs also appear at ±100 kHz from the RF carrier. Harmonics

of all spurs mentioned also appear. With the lowest spur setting

enabled, the spurs are attenuated into the noise floor.

PRESCALER

The prescaler limits the INT value. With P = 4/5, NMIN = 31.

With P = 8/9, NMIN = 91.

The prescaler can also influence the phase noise performance. If

INT < 91, use a prescaler of 4/5. For applications where INT > 91,

use P = 8/9 for optimum noise performance.

FILTER DESIGN—ADISIMPLL

A filter design and analysis program is available to help users

implement their PLL design. Visit www.analog.com/ADIsimPLL

for a free download of the ADIsimPLL™ software. The software

designs, simulates, and analyzes the entire PLL frequency domain

and time domain response. Various passive and active filter

architectures are allowed.

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