ADF4252BCPZ-R7 datasheet(26/30 Pages) AD

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ADF4252

Data Sheet

Rev. E | Page 26 of 30

DEVICE PROGRAMMING AFTER INITIAL POWER-UP

After initially applying power to the supply pins, there are three

ways to operate the device.

RF AND IF SYNTHESIZERS OPERATIONAL

All registers must be written to when powering up both the RF

and IF synthesizer.

RF SYNTHESIZER OPERATIONAL, IF POWER-DOWN

It is necessary to write to the R3, R2, R1, and R0 RF registers

when powering up the RF synthesizer only. It is also necessary

to write 0x0026 to R6, and to write all zeros to the R5, R4, and

R3 IF registers.

IF SYNTHESIZER OPERATIONAL, RF POWER-DOWN

It is necessary to write to the R6, R5, R4, and R3 IF registers

when powering up the IF synthesizer only. It is also necessary to

write 0x0023 to R3, and to write all zeros to the R2, R1, and R0

RF registers.

RF SYNTHESIZER: AN EXAMPLE

Program the RF synthesizer as follows:

PFD

OUT

MOD

FRAC

INT



















(4)

where:

RFOUT is the RF frequency output.

INT is the integer division factor.

FRAC is the fractionality.

MOD is the modulus.



















REF

PFD

(5)

where:

REFIN is the reference frequency input.

D is the RF REFIN doubler bit.

R is the RF reference division factor.

For example, in a GSM 1800 system where 1.8 GHz RF

frequency output (RFOUT) is required, a 13 MHz reference

frequency input (REFIN) is available and a 200 kHz channel

resolution (fRES) is required on the RF output.

RES

REF

MOD 

kHz

200

MHz



MOD

Therefore, from Equation 5,

MHz









PFD



















MHz

GHz

FRAC

INT

where INT = 138 and FRAC = 30.

IF SYNTHESIZER: AN EXAMPLE

The IF synthesizer must be programmed as follows:

IFOUT = [(P × B) + A] × fPFD

(6)

where:

IFOUT is the output frequency of the external voltage controlled

oscillator (VCO).

P is the IF prescaler.

B is the B counter value.

A is the A counter value.

Equation 5 applies in this example as well.

For example, in a GSM1800 system, where 540 MHz IF

frequency output (IFOUT) is required, a 13 MHz reference

frequency input (REFIN) is available and a 200 kHz channel

resolution (fRES) is required on the IF output. The prescaler is set

to 16/17. The IF REFIN doubler is disabled.

By Equation 5,

MHz

kHz

200







if R = 65.

By Equation 6,

540 MHz = 200 kHz × [(16 × B) + A]

if B = 168 and A = 12.

MODULUS

The choice of modulus (MOD) depends on the reference signal

(REFIN) available and the channel resolution (fRES) required at

the RF output. For example, a GSM system with 13 MHz REFIN

sets the modulus to 65. This means that the RF output resolution

(fRES) is the 200 kHz (13 MHz/65) necessary for GSM.

REFERENCE DOUBLER AND REFERENCE DIVIDER

There is a reference doubler on-chip, which allows the input

reference signal to be doubled. This is useful for increasing the

PFD comparison frequency. Making the PFD frequency higher

improves the noise performance of the system. Doubling the

PFD frequency usually results in an improvement in noise

performance of 3 dB. It is important to note that the PFD

cannot be operated above 30 MHz due to a limitation in the

speed of the Σ-Δ circuit of the N divider.

12-BIT PROGRAMMABLE MODULUS

Unlike most other fractional-N PLLs, the ADF4252 allows the

user to program the modulus over a 12-bit range. This means that

the user can set up the device in many different configurations

for a specific application, when combined with the reference

doubler and the 4-bit R counter.

For example, in an application that requires 1.75 GHz RF and

200 kHz channel step resolution, the system has a 13 MHz

reference signal.

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