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STM32L010K4 датащи(PDF) 25 Page - STMicroelectronics |
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STM32L010K4 датащи(HTML) 25 Page - STMicroelectronics |
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25 / 91 page ![]() DS12323 Rev 3 25/91 STM32L010F4/K4 Functional overview 28 3.13.2 Low-power timer (LPTIM) LPTIM1 has an independent clock and is running also in Stop mode if it is clocked by LSE, LSI or an external clock. This timer is able to wakeup the STM32L010F4/K4 from Stop mode. LPTIM1 supports the following features: • 16-bit up counter with 16-bit autoreload register • 16-bit compare register • Configurable output: pulse, PWM • Continuous / one shot mode • Selectable software / hardware input trigger • Selectable clock source – Internal clock source: LSE, LSI, HSI or APB clock – External clock source over LPTIM1 input (working even with no internal clock source running, used by the pulse counter application) • Programmable digital glitch filter • Encoder mode 3.13.3 SysTick timer This timer is dedicated to the OS, but can also be used as a standard downcounter. It is based on a 24-bit downcounter with autoreload capability and a programmable clock source. It features a maskable system interrupt generation when the counter reaches ‘0’. 3.13.4 Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 37 kHz internal RC and, as it operates independently of the main clock, it can operate in Stop and Standby modes. IWDG can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. The counter can be frozen in debug mode. 3.13.5 Window watchdog (WWDG) The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.14 Communication interfaces 3.14.1 I2C bus One I2C interface (I2C1) can operate in multimaster or slave mode. The I2C interface can support Standard mode up to 100 kbit/s and Fast mode (Fm) up to 400 kbit/s. The I2C interface supports 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). |
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