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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SPC58NH84C5 датащи(PDF) 107 Page - STMicroelectronics |
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SPC58NH84C5 датащи(HTML) 107 Page - STMicroelectronics |
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107 / 147 page  DS12304 Rev 5 107/147 SPC58EHx, SPC58NHx Electrical characteristics 109 • Output parameters are valid for CL = 25 pF, where CL is the external load to the device (lumped). The internal package capacitance is accounted for, and does not need to be subtracted from the 25 pF value. • Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may cause incorrect operation. • Programming the IBFD register (I2C bus Frequency Divider) with the maximum frequency results in the minimum output timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the pre-scale and division values programmed in the IBC field of the IBFD register. Figure 41. I2C input/output timing Table 60. I2C output timing specifications — SCL and SDA No. Symbol C Parameter Value Unit Min Max 1 — CC D Start condition hold time 6 — PER_CLK Cycle(1) 2 — CC D Clock low time 10 — PER_CLK Cycle 3 — CC D Bus free time between Start and Stop condition 4.7 — µs 4 — CC D Data hold time 7 — PER_CLK Cycle 5 — CC D Clock high time 10 — PER_CLK Cycle 6 — CC D Data setup time 2 — PER_CLK Cycle 7 — CC D Start condition setup time (for repeated start condition only) 20 — PER_CLK Cycle 8 — CC D Stop condition setup time 10 — PER_CLK Cycle 1. PER_CLK is the SoC peripheral clock, which drives the I2C BIU and module clock inputs. See the Clocking chapter in the device reference manual for more detail. SCL SDA 1 2 4 5 6 7 3 8 |
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