SPC58NH84C5 datasheet(31/147 Pages) STMICROELECTRONICS

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DS12304 Rev 5

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SPC58EHx, SPC58NHx

Electrical characteristics

4.8

I/O pad specification

The following table describes the different pad type configurations.

Note:

Each I/O pin on the device supports specific drive configurations. See the signal description

table in the device reference manual for the available drive configurations for each I/O pin.

PMC_DIG_VSIO register has to be configured to select the voltage level (3.3 V or 5.0 V) for

each IO segment.

Logic level is configurable in running mode while it is CMOS not-configurable in STANDBY

for LP (low power) pads, so if a LP pad is used to wakeup from STANDBY, it should be

configured as CMOS also in running mode in order to prevent device wrong behavior in

STANDBY.

The SPC58EHx, SPC58NHx microcontroller has many GPIOs in double bonding; this

feature is in place for all packages but FPBGA386. Indeed some IO PADS are bonded

together within the package, in order to provide different alternative functions to the same

pin/ball.

The application shall enable only one pad at a time for each pin/ball in double bonding, in

order to avoid high current consumption, due to electrical contention, and reliability issues

of the pad drivers.

Refer to the SPC58EHx, SPC58NHx IO_ definition document, where double bonded

ball/pins are clearly identified, paying attention during software design to strictly avoid the

above situation depicted of electrical contention.

4.8.1

I/O input DC characteristics

The following table provides input DC electrical characteristics, as described in Figure 3.

Table 9. I/O pad specification descriptions

Pad type

Description

Weak configuration

Provides a good compromise between transition time and low electromagnetic emission.

Medium configuration

Provides transition fast enough for the serial communication channels with controlled

current to reduce electromagnetic emission.

Strong configuration

Provides fast transition speed; used for fast interface.

Very strong

configuration

Provides maximum speed and controlled symmetric behavior for rise and fall transition.

Used for fast interface including Ethernet, SDMMC, OctalSPI and FlexRay interfaces

requiring fine control of rising/falling edge jitter.

Ultra strong

configuration

Provides very high speed interfaces till 125 MHz. Used for fast interface including

Ethernet, SDMMC, OctalSPI and FlexRay interfaces.

Input only pads

These low input leakage pads are associated with the ADC channels.

Standby pads

These pads (LP pads) are active during STANDBY. They are configured in CMOS level

logic and this configuration cannot be changed. Moreover, when the device enters the

STANDBY mode, the pad-keeper feature can be activated for LP pads. It means that:

– if the pad voltage level is above the pad keeper high threshold, a weak pull-up resistor

is automatically enabled

– if the pad voltage level is below the pad keeper low threshold, a weak pull-down resistor

is automatically enabled.

For the pad-keeper high/low thresholds please consider (VDD_HV_IO_MAIN / 2) +/-20%.

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