SPC58NH84C5 datasheet(49/147 Pages) STMICROELECTRONICS

49 / 147 page

DS12304 Rev 5

49/147

SPC58EHx, SPC58NHx

Electrical characteristics

4.10.2

PLL1

PLL1 is a frequency modulated PLL with Spread Spectrum Clock Generation (SSCG)

support.

4.10.3

PLL_ETH

This PLL provides a clock that is not frequency modulated to Ethernet1 IP for managing

Delay-on-Source for its Tx clock. The input sources for PLL_ETH are:

XOSC

ETH1_RX clock div1/div5 based on speed

Divided clock from PLL0, derived from CGM_AC2_DC1

Note:

PLL_ETH is another instance of PLL0 so the electrical characteristics for PLL_ETH are

similar to PLL0, the main difference is PHI0 has to be programmed always to generate

500 MHz.

Table 21. PLL1 electrical characteristics

Symbol

Parameter

Conditions

Value

Unit

Min

Typ

Max

fPLL1IN

—

PLL1 input clock(1)

—

37.5

—

87.5

MHz

ΔPLL1IN

—

PLL1 input clock duty

cycle(1)

—35

—

fINFIN

—

PLL1 PFD (Phase

Frequency Detector)

input clock frequency

—

37.5

87.5

MHz

fPLL1VCO

PLL1 VCO frequency

—

600

—

1400

MHz

fPLL1PHI0

PLL1 output clock PHI0

—

4.762

—

FSYS(2)

MHz

tPLL1LOCK

PLL1 lock time

—

µs

fPLL1MOD

PLL1 modulation

frequency

—

250

kHz

|δPLL1MOD|CC

PLL1 modulation depth

(when enabled)

Center spread(3)

0.25

—

Down spread

0.5

—

|ΔPLL1PHI0SPJ|

(4)

PLL1_PHI0 single period

peak to peak jitter

fPLL1PHI0 =

200 MHz, 6-sigma

——

500(5)

IPLL1

PLL1 consumption

FINE LOCK state

—

1. PLL1IN clock retrieved directly from either internal PLL0 or external FXOSC clock. Input characteristics are granted when

using internal PPL0 or external oscillator is used in functional mode.

2. Refer to Section 4.3: Operating conditions for the maximum operating frequency.

3. The device maximum operating frequency FSYS (max) includes the frequency modulation. If center modulation is selected,

the FSYS must be below the maximum by MD (Modulation Depth Percentage), such that FSYS(max)=FSYS(1+MD%).

Refer to the Reference Manual for the PLL programming details.

4. Jitter values reported in this table refer to the internal jitter, and do not include the contribution of the divider and the path to

the output CLKOUT pin.

5. 1.25 V±5%, application noise below 40 kHz at VDD_LV pin - no frequency modulation.

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