SPC572L64F2 datasheet(98/112 Pages) STMICROELECTRONICS

98 / 112 page

Package characteristics

SPC572Lx

98/112

DocID027866 Rev 5

4.4.1

General notes for specifications at maximum junction temperature

An estimation of the chip junction temperature, TJ, can be obtained from the equation:

Equation 1 TJ = TA + (RθJA * PD)

where:

TA = ambient temperature for the package (°C)

RθJA = junction-to-ambient thermal resistance (°C/W)

PD = power dissipation in the package (W)

The thermal resistance values used are based on the JEDEC JESD51 series of standards to

provide consistent values for estimations and comparisons. The difference between the

values determined for the single-layer (1s) board compared to a four-layer board that has two

signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal

resistance is not a constant. The thermal resistance depends on the:

•

Construction of the application board (number of planes)

•

Effective size of the board which cools the component

•

Quality of the thermal and electrical connections to the planes

•

Power dissipated by adjacent components

Connect all the ground and power balls to the respective planes with one via per ball. Using

fewer vias to connect the package to the planes reduces the thermal performance. Thinner

planes also reduce the thermal performance. When the clearance between the vias leave the

planes virtually disconnected, the thermal performance is also greatly reduced.

Table 54. Thermal characteristics for eTQFP100(1)

Symbol

Parameter

Conditions

Value

Unit

RθJA

Junction-to-ambient, natural

convection(2)

Four layer board—2s2p

27.9

°C/W

RθJMA

Junction-to-moving-air, ambient(2)

At 200 ft./min., four layer

board—2s2p

22.8

°C/W

RθJB

Junction-to-board(3)

Ring cold plate

11.3

°C/W

RθJCtop

Junction-to-case top(4)

Cold plate

13.0

°C/W

RθJCbotttom CC

Junction-to-case bottom(5)

Cold plate

1.0

°C/W

ΨJT

Junction-to-package top(6)

Natural convection

0.4

°C/W

1. The values are based on simulation; actual data may vary in the given range. The specified characteristics are subject to

change per final device design and characterization. Junction temperature is a function of die size, on-chip power

dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power

dissipation of other components on the board, and board thermal resistance.

2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

5. Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.

6. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2.

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