SPC572L64F2 datasheet(32/112 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC572Lx

32/112

DocID027866 Rev 5

Table 17 shows the VERY STRONG configuration output buffer electrical characteristics.

TPHL/PLH CC

Propagation delay

CL = 25 pF,

4.5 V < VDD_HV_IO < 5.9 V

—

CL = 25 pF,

3.0 V < VDD_HV_IO < 3.6 V

——

CL = 50 pF,

4.5 V < VDD_HV_IO < 5.9 V

——

CL = 50 pF,

3.0 V < VDD_HV_IO <

3.6 V(5)

——

1. All VDD_HV_IO conditions for 4.5 V to 5.5 V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0 V to 3.6 V are valid

for VSIO[VSIO_xx] = 0

2. All values need to be confirmed during device validation.

3. CL is the sum of external capacitance. Device and package capacitances (CIN, defined in Table 12) are to be added to

calculate total signal capacitance (CTOT = CL + CIN).

4. Transition time maximum value is approximated by the following formula: tTR_S(ns) = 4.5 ns + CL(pF) x 0.23 ns/pF.

5. Only for VDD_HV_IO_JTAG segment when VSIO[VSIO_IJ] = 0 or VDD_HV_IO_ETH segment when VSIO[VSIO_IF] = 0

Table 16. STRONG configuration output buffer electrical characteristics (continued)

Symbol

Parameter

Conditions(1)

Value(2)

Unit

Min

Typ

Max

Table 17. VERY STRONG configuration output buffer electrical characteristics

Symbol

Parameter

Conditions(1)

Value(2)

Unit

Min

Typ

Max

ROH_V

PMOS output impedance

VERY STRONG

configuration

VDD_HV_IO = 5.0 V ± 10%,

VSIO[VSIO_xx] = 1,

IOH = 8 mA

CVDD_HV_IO = 3.3 V ± 10%,

VSIO[VSIO_xx] = 0,

IOH = 7 mA(3)

ROL_V

NMOS output impedance

VERY STRONG

configuration

VDD_HV_IO = 5.0 V ± 10%,

VSIO[VSIO_xx] = 1,

IOL = 8 mA

CVDD_HV_IO = 3.3 V ± 10%,

VSIO[VSIO_xx] = 0,

IOL = 7 mA(3)

fMAX_V

Output frequency

VERY STRONG

configuration

VDD_HV_IO = 5.0 V ± 10%,

CL = 25 pF(4)

——

MHz

VSIO[VSIO_xx] = 1,

CL = 15 pF(3),(4)

——

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