SPC572L64F2 datasheet(97/112 Pages) STMICROELECTRONICS

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SPC572Lx

Package characteristics

111

4.4

Thermal characteristics

Table 53 and Table 54 describe the thermal characteristics of the device.

3. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed

the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum

space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.

4. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.

5. To be determined at seating datum plane C.

6. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm.

7. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side.

D1 and E1 are maximum plastic body size dimensions including mold mismatch.

8. Dimensions D2 and E2 show the maximum exposed metal area on the package surface where the exposed pad is located

(if present). It includes all metal protrusions from exposed pad itself. Type of exposed pad is variable depending on

leadframe pad design (T1, T2, T3). End user should verify D2 and E2 dimensions according to specific device application.

9. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of exposed pad which is guaranteed to

be free from resin flashes/bleeds, bordered by internal edge of inner groove.

10. “N” is the number of terminal positions for the specified body size.

11. Tolerance

Table 53. Thermal characteristics for eTQFP80(1)

Symbol

Parameter

Conditions

Value

Unit

RθJA

Junction-to-ambient, natural

convection(2)

Four layer board—2s2p

29.6

°C/W

RθJMA

Junction-to-moving-air, ambient(2)

At 200 ft./min., four layer

board—2s2p

23.5

°C/W

RθJB

Junction-to-board(3)

Ring cold plate

9.6

°C/W

RθJCtop

Junction-to-case top(4)

Cold plate

13.2

°C/W

RθJCbotttom

Junction-to-case bottom(5)

Cold plate

1.0

°C/W

ΨJT

Junction-to-package top(6)

Natural convection

0.4

°C/W

1. The values are based on simulation; actual data may vary in the given range. The specified characteristics are subject to

change per final device design and characterization. Junction temperature is a function of die size, on-chip power

dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power

dissipation of other components on the board, and board thermal resistance.

2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

5. Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.

6. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2.

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