STM32G0 datasheet(23/135 Pages) STMICROELECTRONICS

23 / 135 page

DS12232 Rev 4

23/135

STM32G071x8/xB

Functional overview

Through a specific sequence, this special function configuration of I/Os can be locked, such

as to avoid spurious writing to I/O control registers.

3.11

Direct memory access controller (DMA)

The direct memory access (DMA) controller is a bus master and system peripheral with

single-AHB architecture.

With 7 channels, it performs data transfers between memory-mapped peripherals and/or

memories, to offload the CPU.

Each channel is dedicated to managing memory access requests from one or more

peripherals. The unit includes an arbiter for handling the priority between DMA requests.

Main features of the DMA controller:

•

Single-AHB master

•

Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-to-

peripheral data transfers

•

Access, as source and destination, to on-chip memory-mapped devices such as Flash

memory, SRAM, and AHB and APB peripherals

•

All DMA channels independently configurable:

–

Each channel is associated either with a DMA request signal coming from a

peripheral, or with a software trigger in memory-to-memory transfers. This

configuration is done by software.

–

Priority between the requests is programmable by software (four levels per

channel: very high, high, medium, low) and by hardware in case of equality (such

as request to channel 1 has priority over request to channel 2).

–

Transfer size of source and destination are independent (byte, half-word, word),

emulating packing and unpacking. Source and destination addresses must be

aligned on the data size.

–

Support of transfers from/to peripherals to/from memory with circular buffer

management

–

Programmable number of data to be transferred: 0 to 216 - 1

•

Generation of an interrupt request per channel. Each interrupt request originates from

any of the three DMA events: transfer complete, half transfer, or transfer error.

3.12

DMA request multiplexer (DMAMUX)

The DMAMUX request multiplexer enables routing a DMA request line between the

peripherals and the DMA controller. Each channel selects a unique DMA request line,

unconditionally or synchronously with events from its DMAMUX synchronization inputs.

DMAMUX may also be used as a DMA request generator from programmable events on its

input trigger signals.

3.13

Interrupts and events

The device flexibly manages events causing interrupts of linear program execution, called

exceptions. The Cortex-M0+ processor core, a nested vectored interrupt controller (NVIC)

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