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STM32F730V8 датащи(PDF) 126 Page - STMicroelectronics

номер детали STM32F730V8
подробное описание детали  Arm® Cortex®-M7 32b MCUFPU, 462DMIPS, 64KB Flash /256164KB RAM, USB OTG HS/FS, 18 TIMs, 3 ADCs, 21 com IF
PDF  202 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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STM32F730V8 датащи(HTML) 126 Page - STMicroelectronics

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Electrical characteristics
STM32F730x8
126/202
DS12536 Rev 2
6.3.13
USB OTG HS PHY PLLs characteristics
The parameters given in Table 48 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 16.
6.3.14
USB OTG HS PHY regulator characteristics
The parameters given in Table 50 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 16.
Table 48. USB OTG HS PLL1 characteristics(1)
1. Guaranteed by design.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPLL1_IN
PLL1 input clock
-
12, 12.5, 16, 24, 25
MHz
fPLL1_OUT PLL1 output clock(2)
2. Based on test during characterization.
--
60
-
fVCO_OUT PLL1 VCO output
-
600
-
720
tLOCK
PLL1 lock time(2)
--
-
22
µs
IDD(PLL1)
PLL1 digital power consumption
-
-
-
1.8
mA
IDDA(PLL1) PLL1 analog power consumption
-
-
-
2.75
Table 49. USB OTG HS PLL2 characteristics(1)
1. Guaranteed by design.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPLL2_IN
PLL2 input clock
-
-
60
-
MHz
fPLL2_OUT PLL2 output clock(2)
2. Based on test during characterization.
--
480
-
fVCO_OUT PLL2 VCO output
-
-
480
-
tLOCK
PLL2 lock time(2)
--
-
91
µs
IDD(PLL2)
PLL2 digital power consumption
-
-
-
2.1
mA
IDDA(PLL2) PLL2 analog power consumption
-
-
-
1.5
Table 50. USB OTG HS PHY regulator characteristics(1)
1. Based on test during characterization.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD12OTGHS
1.2 V internal voltage on VDD12OTGHS
-1.18
1.2
1.24
V
CEXT
External capacitor on VDD12OTGHS
-
1.1
2.2
3.3
µF
IDDPHYHSREG
Regulator power consumption
-
100
120
125
µA



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