STM32F730V8 datasheet(47/202 Pages) STMICROELECTRONICS

47 / 202 page

DS12536 Rev 2

47/202

STM32F730x8

Functional overview

The AES peripheral supports:

•

Encryption/Decryption using AES Rijndael Block Cipher algorithm

•

NIST FIPS 197 compliant implementation of AES encryption/decryption algorithm

•

128-bit and 256-bit register for storing the encryption, decryption or derivation key

(4x 32-bit registers)

•

Electronic codebook (ECB), Cipher block chaining (CBC), Counter mode (CTR), Galois

Counter Mode (GCM), Galois Message Authentication Code mode (GMAC) and Cipher

Message Authentication Code mode (CMAC) supported.

•

Key scheduler

•

Key derivation for decryption

•

128-bit data block processing

•

128-bit, 256-bit key length

•

1x32-bit INPUT buffer and 1x32-bit OUTPUT buffer.

•

One 128-bit Register for the initialization vector when AES is configured in CBC mode

or for the 32-bit counter initialization when CTR mode is selected, GCM mode or

CMAC mode.

•

Automatic data flow control with support of direct memory access (DMA) using 2

channels, one for incoming data, and one for outcoming data.

•

Suspend a message if another message with a higher priority needs to be processed

3.33

General-purpose input/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain,

with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)

or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog

alternate functions. All GPIOs are high-current-capable and have speed selection to better

manage internal noise, power consumption and electromagnetic emission.

The I/O configuration can be locked if needed by following a specific sequence in order to

avoid spurious writing to the I/Os registers.

A Fast I/O handling allows a maximum I/O toggling up to 108 MHz.

3.34

Analog-to-digital converters (ADCs)

Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16

external channels, performing conversions in the single-shot or scan mode. In the scan

mode, an automatic conversion is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

•

Simultaneous sample and hold

•

Interleaved sample and hold

The ADC can be served by the DMA controller. An analog watchdog feature allows very

precise monitoring of the converted voltage of one, some or all selected channels. An

interrupt is generated when the converted voltage is outside the programmed thresholds.

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