STM32F730V8 datasheet(29/202 Pages) STMICROELECTRONICS

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DS12536 Rev 2

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STM32F730x8

Functional overview

On the STM32F7x3xx devices, the USB OTG HS sub-system uses one or two additional

power supply pins depending on the package:

•

The VDD12OTGHS pin is the output of PHY HS regulator (1.2V). An external capacitor

of 2.2 µF must be connected on the VDD12OTGHS pin.

•

On the LQFP100 only, a second power pin VDDPHYHS is used to supply the USB

OTG PHY HS and associated GPIOs.The VDDPHYHS follows the same rules provided

for the VDDUSB power pin.

3.15

Power supply supervisor

3.15.1

Internal reset ON

On packages embedding the PDR_ON pin, the power supply supervisor is enabled by

holding PDR_ON high. On the other packages, the power supply supervisor is always

enabled.

The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry

coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and

ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is

reached, the option byte loading process starts, either to confirm or modify default BOR

thresholds, or to disable BOR permanently. Three BOR thresholds are available through

option bytes. The device remains in reset mode when VDD is below a specified threshold,

VPOR/PDR or VBOR, without the need for an external reset circuit.

The device also features an embedded programmable voltage detector (PVD) that monitors

the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be

generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is

higher than the VPVD threshold. The interrupt service routine can then generate a warning

message and/or put the MCU into a safe state. The PVD is enabled by software.

3.15.2

Internal reset OFF

This feature is available only on packages featuring the PDR_ON pin. The internal power-on

reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.

An external power supply supervisor should monitor VDD and NRST and should maintain

the device in reset mode as long as VDD is below a specified threshold. PDR_ON should be

connected to VSS. Refer to Figure 8: Power supply supervisor interconnection with internal

reset OFF.

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