STM32F730V8 datasheet(25/202 Pages) STMICROELECTRONICS

25 / 202 page

DS12536 Rev 2

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STM32F730x8

Functional overview

3.8

Flexible memory controller (FMC)

The Flexible memory controller (FMC) includes three memory controllers:

•

The NOR/PSRAM memory controller

•

The NAND/memory controller

•

The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller

The main features of the FMC controller are the following:

•

Interface with static-memory mapped devices including:

–

Static random access memory (SRAM)

–

NOR Flash memory/OneNAND Flash memory

–

PSRAM (4 memory banks)

–

NAND Flash memory with ECC hardware to check up to 8 Kbytes of data

•

Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories

•

8-, 16-, 32-bit data bus width

•

Independent Chip Select control for each memory bank

•

Independent configuration for each memory bank

•

Write FIFO

•

Read FIFO for SDRAM controller

•

The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is

HCLK/2

LCD parallel interface

The FMC can be configured to interface seamlessly with most graphic LCD controllers. It

supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to

specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-

effective graphic applications using LCD modules with embedded controllers or high

performance solutions using external controllers with dedicated acceleration.

3.9

Quad-SPI memory interface (QUADSPI)

All the devices embed a Quad-SPI memory interface, which is a specialized communication

interface targetting Single, Dual or Quad-SPI Flash memories. It can work in:

•

Direct mode through registers

•

External Flash status register polling mode

•

Memory mapped mode.

Up to 256 Mbytes of external Flash are memory mapped, supporting 8, 16 and 32-bit

access. The code execution is supported.

The opcode and the frame format are fully programmable. The communication can be either

in Single Data Rate or Dual Data Rate.

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