STM32F730V8 datasheet(92/202 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F730x8

92/202

DS12536 Rev 2

Ambient temperature for 6 suffix

version

Maximum power dissipation

− 40

°C

Low power dissipation(10)

− 40

105

Ambient temperature for 7 suffix

version

Maximum power dissipation

− 40

105

°C

Low power dissipation(10)

− 40

125

Junction temperature range

6 suffix version

− 40

105

°C

7 suffix version

− 40

125

1. The over-drive mode is not supported at the voltage ranges from 1.7 to 2.1 V.

2. 216 MHz maximum frequency for 6 suffix version (200 MHz maximum frequency for 7 suffix version).

3. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.15.2:

Internal reset OFF).

4. When the ADC is used, refer to Table 67: ADC characteristics.

5. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V.

6. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA

can be tolerated during power-up and power-down operation.

7. The over-drive mode is not supported when the internal regulator is OFF.

8. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled

9. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax.

10. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax.

Table 16. General operating conditions (continued)

Symbol

Parameter

Conditions(1)

Min

Typ

Max

Unit

Table 17. Limitations depending on the operating power supply range

Operating

power supply

range

ADC operation

Maximum Flash

memory access

frequency with

no wait states

(fFlashmax)

Maximum HCLK

frequency vs Flash

memory wait states

(1)(2)

I/O operation

Possible Flash

memory

operations

VDD =1.7 to

2.1 V(3)

Conversion time

up to 1.2 Msps

20 MHz

180 MHz with 8 wait

states and over-drive

OFF

No I/O

compensation

8-bit erase and

program

operations only

VDD = 2.1 to

2.4 V

Conversion time

up to 1.2 Msps

22 MHz

216 MHz with 9 wait

states and over-drive

No I/O

compensation

16-bit erase and

program

operations

VDD = 2.4 to

2.7 V

Conversion time

up to 2.4 Msps

24 MHz

216 MHz with 8 wait

states and over-drive

I/O compensation

works

16-bit erase and

program

operations

VDD = 2.7 to

3.6 V(4)

Conversion time

up to 2.4 Msps

30 MHz

216 MHz with 7 wait

states and over-drive

I/O compensation

works

32-bit erase and

program

operations

1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is

required.

2. Thanks to the ART accelerator on ITCM interface and L1-cache on AXI interface, the number of wait states given here

does not impact the execution speed from Flash memory since the ART accelerator or L1-cache allows to achieve a

performance equivalent to 0-wait state program execution.

3. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.15.2:

Internal reset OFF).

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