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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM32F730V8 датащи(PDF) 45 Page - STMicroelectronics |
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STM32F730V8 датащи(HTML) 45 Page - STMicroelectronics |
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45 / 202 page  DS12536 Rev 2 45/202 STM32F730x8 Functional overview 49 3.29 Universal serial bus on-the-go full-speed (OTG_FS) The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: • Combined Rx and Tx FIFO size of 1.28 Kbytes with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints • 12 host channels with periodic OUT support • Software configurable to OTG1.3 and OTG2.0 modes of operation • USB 2.0 LPM (Link Power Management) support • Internal FS OTG PHY support • HNP/SNP/IP inside (no need for any external resistor) • BCD support For the OTG/Host modes, a power switch is needed in case bus-powered devices are connected 3.30 Universal serial bus on-the-go high-speed (OTG_HS) The devices embed an USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 Mbit/s). The STM32F730x8 devices feature a UTMI low-pin interface (ULPI) for high-speed operation (480 Mbit/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required. The STM32F730x8 devices feature an integrated PHY HS. The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has a software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: • Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 8 bidirectional endpoints • 16 host channels with periodic OUT support • Software configurable to OTG1.3 and OTG2.0 modes of operation • USB 2.0 LPM (Link Power Management) support |
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