LT4295 datasheet(15/50 Pages) AD

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LTC9101-1/

LTC9102/LTC9103

Rev. 0

For more information www.analog.com

PIN FUNCTIONS

AUTO (Pin 20): Auto Mode Input, Active High. Auto mode

allows the LTC9101-1 to detect, classify, and power up

valid PDs without host interaction. AUTO determines the

state of the internal registers when the LTC9101-1 is

reset or comes out of UVLO (see LTC9101-1 Software

Programming documentation). See Auto Mode Maximum

PSE Power for details. The state of these register bits can

subsequently be changed via the I2C interface. Internally

pulled down to DGND. The AUTO pin is ignored when

a custom configuration package is present. See Stored

Configurations for details.

MSD (Pin 21): Maskable Shutdown Input, Active Low.

When pulled low, all ports that have their corresponding

mask bit set in the mconf register (0x17) will be reset.

Internal filtering of MSD prevents glitches less than 1µs

wide from resetting ports. The MSD Pin Mode register

can configure MSD polarity. Internally pulled up to VDD.

DGND (Pins 22, 25): Digital Ground. DGND should be

connected to the return from the VDD supply.

LTC9102/LTC9103 COMMON

CAP3 (Pin 1): Analog Internal 3.3V Power Supply Bypass

Capacitor. Connect a 1μF ceramic cap to VEE. A 3.3V power

supply may be connected to this pin to improve power

supply efficiency. The EXT3 pin must be pulled to CAP3

to shut off the internal 3.3V regulator if power is supplied

externally. Do not source or sink current from this pin. Do

not connect to CAP3 except as explicitly instructed in ADI

documentation (e.g., strapping LTC9102/LTC9103 pins

and terminating the serial interface).

EXT3 (Pin 2): External 3.3V Enable. Connect the EXT3

pin to CAP3 to shut off the internal 3.3V regulator when

power is supplied externally. Float or connect to VEE for

internal regulator operation.

ID[1:0] (Pins 52, 51 respectively): Transceiver ID. Sets

the address of the LTC9102/LTC9103 on the multidrop

high-speed data interface. ID numbering must start at

00b. Tie high by connecting to CAP3. Tie low by connect-

ing to VEE. See Device Configuration section for details.

PWRIN (Pin 55): Startup Regulator Bypass and External

Low Voltage Supply Input. Power for the internal 4.3V

and 3.3V internal supplies. An internal regulator maintains

the voltage of this pin above 6V. An external resistor or

supply may be connected to this node to improve the

power efficiency of the LTC9102/LTC9103. Connect a 1µF

capacitor between this pin and VEE.

AGND (Pin 56): Analog Ground.

PWRMD[1:0] (Pins 57, 58 Respectively): Maximum

Power Mode Input. Connect PWRMD0 of the LTC9102/

LTC9103 with ID[1:0] = 00b to VEE with configuration

resistor RPWRMD. When the LTC9101-1 is reset with AUTO

pin high, RPWRMD selects initial maximum power alloca-

tion values for every port in the chipset; the system power

supply must be sized to support all ports outputting up to

RPWRMD. When auto mode is enabled, the chipset runs

independently as a PoE PSE. The chipset will detect and

class all ports and grant power to each port up to RPWRMD

setting. The PWRMD0 pin of LTC9102/LTC9103s with ID

pins set to 01b, 10b, and 11b must be left floating. The

PWRMD1 pin of all LTC9102/LTC9103s must be left float-

ing. See Auto Mode Maximum PSE Power for RPWRMD

options and details. The PWRMD pins are ignored when

a custom configuration package is present. See Stored

Configurations for details.

CAP4 (Pin 59): Analog Internal 4.3V Power Supply

Bypass Capacitor. Connect a 1μF ceramic cap to VEE. Do

not source or sink current from this pin.

VEE (Pins 60, 65): Main PoE Supply Input. Connect to a

–51V to –57V supply, relative to AGND. Voltage depends

on PSE Type (Type 3 or 4).

DNA (Pin 61): Data Transceiver Negative Input Output

(Analog). Connect to DND through a data transformer.

DPA (Pin 62): Data Transceiver Positive Input Output

(Analog). Connect to DPD through a data transformer.

CNA (Pin 63): Clock Transceiver Negative Input Output

(Analog). Connect to CND through a data transformer.

CPA (Pin 64): Clock Transceiver Positive Input Output

(Analog). Connect to CPD through a data transformer.

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