LT4295 datasheet(39/50 Pages) AD

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LTC9101-1/

LTC9102/LTC9103

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

capacitor of at least 47μF, 100V and a bulk TVS are also

recommended per system.

LTC9102/LTC9103 Low Voltage Power Supplies

The LTC9102/LTC9103 includes internal voltage regula-

tors that generate low voltage supplies directly from the

main PoE power supply. At startup, an internal regula-

tor generates 6V at PWRIN, drawing power from AGND.

Internal 4.3V and 3.3V rails are sub-regulated from

PWRIN. The PWRIN pin requires a local 1μF, 100V bypass

capacitor.

Pull-up resistors can be connected from PWRIN to AGND

to dissipate heat outside the LTC9102/LTC9103 package.

Optionally, an external power supply can be connected

to PWRIN to override the startup regulator and reduce

power dissipation.

Figure 26 shows a pull-up resistor configuration with the

internal 3.3V regulator. Bypass resistors R1, R2, R3, and

R4 draw heat away from the LTC9102s/LTC9103s. Note

that the voltage of the PWRIN pin changes based on the

LTC9102/LTC9103 operating mode and its correspond-

ing current consumption. If more current is consumed

than the bypass resistors provide, the startup regulator

maintains the voltage at 6V typical. The LTC9102 can

operate without the pull-up resistors in space-constrained

applications.

In applications with an external PWRIN supply, a 6.5V reg-

ulator provides an optimum voltage to override the inter-

nal 6V start-up regulator, while minimizing the LTC9102

device heating. The external supply may be shared across

multiple LTC9102s/LTC9103s.

A 3.3V power supply can be connected directly to the

CAP3 pin, as shown in Figure 27. This provides the most

power efficient sleep mode. When supplying external 3.3V

power, tie the EXT3 pin to CAP3. This will disable the

internal 3.3V regulator and prevent power back-feed. The

3.3V regulator must power up within tCAP3EXT specified in

the electrical characteristics table.

Digital Power Supply

VDD provides digital power for the LTC9101-1 proces-

sor. A ceramic decoupling cap of at least 0.1μF should

be placed from each VDD to DGND, as close as practical

to each LTC9101-1. In addition, each LTC9101-1 must

include a bulk cap of 10µF for robust surge immunity.

A 1.2V core voltage supply is generated internally and

requires a 1µF ceramic decoupling cap between the CAP1

pin and DGND and between CAP2 and DGND.

In systems using ADI’s proprietary isolation, VDD should

be delivered by the host controller’s non-isolated 3.3V

supply. To maintain required isolation, LTC9102/LTC9103

AGND and LTC9101-1 DGND must not be connected.

If using the direct connection scheme, the LTC9101-1

DGND must be connected to LTC9102/LTC9103 VEE.

Main PoE Power Supply

VEE is the main isolated PoE supply that provides power

to the PDs. Because it supplies a relatively large amount

of power and is subject to significant current transients,

it requires more design care than a simple logic supply.

For minimum IR loss and best system efficiency, set VEE

near maximum amplitude (57V), leaving enough margin

to account for transient over or undershoot, temperature

drift, and the line regulation specifications of the particular

power supply used.

A bypass capacitor and a transient voltage suppressor(TVS)

between each LTC9102/LTC9103 AGND and VEE are very

important for reliable operation. If a short circuit occurs

at one of the output ports it can take as long as 1μs for

the LTC9102/LTC9103 to begin regulating the current.

During this time the current is limited only by the small

impedances in the circuit; a high current spike typically

occurs, causing a voltage transient on the VEE supply and

possibly causing the LTC9101-1/LTC9102/LTC9103 to

reset due to a UVLO fault. A 1μF, 100V X7R capacitor

and a SMAJ58A near each LTC9102/LTC9103 are recom-

mended to minimize spurious resets. An electrolytic bulk

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