LT4295 datasheet(14/50 Pages) AD

14 / 50 page

LTC9101-1/

LTC9102/LTC9103

Rev. 0

For more information www.analog.com

PIN FUNCTIONS

LTC9101-1

CFG[2:0] (Pins 3, 2, 1 Respectively): Device Configuration

Inputs. Tie the configuration pins high or low to set num-

ber of ports, channels per port, and number of connected

LTC9102/LTC9103s. See Device Configuration for details.

CFG[0] is ignored when a custom configuration package is

present. See Stored Configurations for details.

AD[3:2] (Pins 6, 5 Respectively): I2C Address Bits 3 to

2. Tie the address pins high or low to set the base I2C

serial address. The base address will be (010A3A200)b.

Internally pulled up to VDD. See Bus Addressing for details.

CAP[2:1] (Pins 7, 23 Respectively): Core Power Supply

Bypass Capacitors. Connect each pin to a 1μF capacitance

to DGND for the internal 1.2V regulator bypass. Do not

use other capacitor values. Do not source or sink current

from this pin.

CPD (Pin 8): Clock Transceiver Positive Input Output

(Digital). Connect to CPA through a data transformer.

CND (Pin 9): Clock Transceiver Negative Input Output

(Digital). Connect to CNA through a data transformer.

DPD (Pin 10): Data Transceiver Positive Input Output

(Digital). Connect to DPA through a data transformer.

DND (Pin 11): Data Transceiver Negative Input Output

(Digital). Connect to DNA through a data transformer.

VDD (Pins 12, 19, 24): VDD IO Power Supply. Connect

to a 3.3V power supply relative to DGND. Each VDD pin

must be locally bypassed with at least a 0.1µF capacitor.

A 10µF bulk capacitor must be connected across VDD for

increased surge immunity.

4PVALID (Pin 13): 4-Pair Valid Input, Active Low. When

low, the LTC9101-1/LTC9102/LTC9103 will not apply

power to a port unless both pairsets present a valid signa-

ture. When high, the LTC9101-1/LTC9102/LTC9103 will

power any pairset presenting a valid signature, regard-

less of the other pairset. Ports in 2-pair or AT mode are

unaffected by 4-Pair Valid setting. Internally pulled down

to DGND. 4PVALID pin is ignored when a custom con-

figuration package is present. See Stored Configurations

for details.

RESET (Pin 14): Reset Input, Active Low. When RESET

is low, the LTC9101-1/LTC9102/LTC9103 is held inactive

with all ports off and all internal registers reset. When

RESET is pulled high, the LTC9101-1/LTC9102/LTC9103

begins normal operation. RESET can be connected to an

external capacitor or RC network to provide a power turn-

on delay. Internal filtering of RESET prevents glitches less

than 1µs wide from resetting the LTC9101-1/LTC9102/

LTC9103. Internally pulled up to VDD.

INT (Pin 15): Interrupt Output, Open Drain. INT will

pull low when any one of several events occur in the

LTC9101-1. It will return to a high impedance state when

bits 6 or 7 are set in the Reset PB register (0x1A). The

INT signal can be used to generate an interrupt to the

host processor, eliminating the need for continuous soft-

ware polling. Individual INT events can be disabled using

the Int Mask register (0x01). See LTC9101-1 Software

Programming documentation for more information. INT

is only updated between I2C transactions.

SDAOUT (Pin 16): Serial Data Output, Open Drain Data

Output for the I2C Serial Interface Bus. The LTC9101-1

uses two pins to implement the bidirectional SDA func-

tion to simplify opto isolation of the I2C bus. To imple-

ment a standard bidirectional SDA pin, tie SDAOUT and

SDAIN together. See Applications Information for more

information.

SDAIN (Pin 17): Serial Data Input. High impedance data

input for the I2C serial interface bus. The LTC9101-1 uses

two pins to implement the bidirectional SDA function to

simplify opto isolation of the I2C bus. To implement a stan-

dard bidirectional SDA pin, tie SDAOUT and SDAIN together.

See Applications Information for more information.

SCL (Pin 18): Serial Clock Input. High impedance clock

input for the I2C serial interface bus. The SCL pin should

be connected directly to the I2C SCL bus line. SCL must

be tied high if the I2C serial interface bus is not used.

LT4295 датащи(PDF) 14 Page - Analog Devices

LT4295 датащи(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

датащи скачать

ссылки URL