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LTC9101-1/

LTC9102/LTC9103

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

As the surge dissipates, the LTC9102/LTC9103 quickly

turns the MOSFET back on in a safe, current limited

manner while minimizing power disruption to the PD.

The LTC9102/LTC9103 fast MOSFET turn off and power

recovery better support both IEEE compliant PDs and PDs

with lower bulk capacitance in high reliability applications.

Port Fault vs Channel Fault

The tCUT, tLIM and tDIS timers are maintained on a per-

channel basis. When any channel timer expires, a deter-

mination is made to remove power from both, one, or

neither channel of the port.

Optional behavior is allowed by the 802.3bt standard

when faults occur on single-signature PDs. This option

allows a single-signature PD to remain powered on pair-

set X, even if a fault occurs on pairset Y. The fault2Pn bit,

when set, enables this optional behavior. This behavior is

not recommended for normal operation, as a fault in the

PD or cabling is indicative of imminent PD or cable failure.

In 2-pair mode fault2Pn has no effect.

Table 13. Channel Fault Effect on Port/Channel State

PD CON-

FIGURATION

fault2Pn

BIT

FAULT RESULT:

TURN OFF PORT OR CHANNEL

tCUT**

tLIM

tDIS

Single

Port

Port*

Channel

Dual

Channel

*If tDIS Expires on Both Channels

**Port power policing (PCUT-4P) raises a tCUT event. When enabled, port

power policing removes power from the port regardless of

fault2Pn

configuration.

Fault Telemetry

As discussed in the preceding sections, faults may occur

on one or both channels, resulting in power removal on

one or both channels. The fault event registers have tra-

ditionally been implemented at the port level. In order

to trace faults to the offending channel, a second layer

of fault registers have been added to the LTC9101-1/

The IHOLD-2P threshold is set automatically in auto mode

and is set by the user in semi-auto and manual modes.

When powering a single-signature PD assigned Class 0 to

Class 4 over a single channel, set the IHOLD-2P threshold

to 7.5mA (typ) via the Disconnect Configuration bit. In all

other cases, set the IHOLD-2P threshold to 3.5mA (typ).

A disconnect timer (tDIS) counts up whenever channel

current is below the IHOLD-2P threshold, indicating that the

PD has been disconnected. If the appropriate tDIS timer(s)

expire, the port or channel (Table 13) will be turned off

and the corresponding tDIS faults are set. If the current

increases above IHOLD-2P before the tDIS timer expires, the

timer(s) reset. As long as the PD exceeds the minimum

current level before tDIS expires, it will remain powered.

Although not recommended, the DC disconnect fea-

ture can be disabled by clearing the corresponding DC

Disconnect Enable bits. Disabling the DC disconnect

feature forces the LTC9101-1/LTC9102/LTC9103 out of

compliance with the IEEE standard. A powered port will

stay powered after the PD is removed; the still-powered

port may be subsequently connected to a non-PoE data

device, potentially causing damage.

The LTC9101-1/LTC9102/LTC9103 does not include AC

disconnect circuitry. AC disconnect is not a supported

feature of 802.3bt.

Fast Surge Recovery

High reliability systems demand excellent surge recov-

ery. It is increasingly important for a PSE to minimize

power disruption to the PDs during extreme power tran-

sients. Furthermore, PDs that do not meet minimum bulk

capacitance requirements are particularly vulnerable to

power brownouts with traditional PSE solutions. The

LTC9101-1/LTC9102/LTC9103 provides an improved

hot swap responsiveness with excellent recovery from

surge events.

During a surge event, the LTC9102/LTC9103 GATE pin

quickly turns off the external MOSFET current flow to

protect the PSE, the MOSFET, and downstream circuitry.

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