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LTC9101-1/

LTC9102/LTC9103

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

9101123 F30

AGND

VEE

SENSEn

VSSKn

GATEn

OUTn

PORT

S1B

1µF

100V

LTC9102/LTC9103

SMAJ58A

CBULK

TVSBULK

VEE

0.1µF

X7R

100V

RSENSEn

AGND

Figure 30. LTC9102/LTC9103 Surge Protection

Table 16. Component Selection for PSE Maximum Class

PSE CLASS

SENSE RESISTOR

HOT SWAP MOSFET

FUSE

ETHERNET TRANSFORMER

Class 3

100mΩ, 1%, 50mW

PSMN075-100MSE

SF-0603HI075F-2

7490220120

Class 4

100mΩ, 1%, 100mW

PSMN075-100MSE

SF-0603HI100F-2

7490220121

Class 6

100mΩ, 1%, 100mW

PSMN040-100MSE

SF-0603HI100F-2

7490220121

Class 8

100mΩ, 1%, 200mW

PSMN040-100MSE

SF-0603HI150F-2

7490220122

TO FET(Qn)

VEE

RSENSEn

SENSEn

VSSKn

9101123 F31

Figure 31. RSENSE Kelvin Connections

The data-lines require impedance matched traces to each

LTC9102/LTC9103. The data bus termination resistors must

be located at the LTC9102/LTC9103 farthest away from the

isolation transformers. For isolated applications, the DC

biasing resistors must connect to the LTC9102/LTC9103

CAP3 pin, farthest away from the isolation transformers. As

shown in Figure 28 and Figure 29, design the interface with

100Ω differential transmission lines, and terminate 100Ωs

differentially. Limit the high-speed data interface line length

to 16 inches. Minimize the transmission stubs between the

LTC9102s/LTC9103s and the high-speed data interface.

LAYOUT REQUIREMENTS

Strict adherence to board layout, parts placement and

routing requirements is critical for IEEE compliance, para-

metric measurement accuracy, system robustness and

thermal dissipation. Refer to the DC3160A-KIT demo kit

for example layout references.

Kelvin Sense

Proper connection of the port current Kelvin sense lines is

important for current threshold accuracy and IEEE compli-

ance. Refer to Figure 31 for an example layout of these Kelvin

sense lines. The LTC9102/LTC9103 VSSKn pin is Kelvin con-

nected to the sense resistor (VEE side) pad and is not other-

wise connected to VEE copper areas. Similarly, the LTC9102/

LTC9103 SENSEn pin is Kelvin connected to the sense resis-

tor (SENSEn side) pad and is not otherwise connected in the

power path. Figure 31 shows the two Kelvin traces from the

LTC9102/LTC9103 to the sense resistor (RSENSEn).

High-Speed Data Interface

The LTC9101-1/LTC9102/LTC9103 chipset communi-

cates across a proprietary high-speed, multi-drop data

interface. This allows for a single LTC9101-1 to control

up to four LTC9102s/LTC9103s.

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