AD4134 datasheet(29/92 Pages) AD

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Data Sheet

AD4134

THEORY OF OPERATION

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Rev. 0 | 29 of 92

Figure 59 shows a simplified signal path of one of the four Σ-Δ ADC

channels of the AD4134. In a typical operation, the CTSD modula-

tor oversamples the analog input signal at the modulator sampling

frequency at MCLK. The ADC quantization noise is modulated to

the higher frequency band during this process. The oversampled

modulator output is then decimated through an ASRC and digital

filter. The decimation removes the additional bandwidth caused by

oversampling along with the shaped quantization. The result is a

high precision data output from the digital filter at the user defined

ODR.

Figure 59. Signal Path Overview

CONTINUOUS TIME SIGMA-DELTA

MODULATOR

Almost all of the contemporary precision ADCs are designed with a

switched capacitor-based sample-and-hold circuit. The sample-and-

hold circuit is an essential part of the successive approximation

reduce the aperture time and maintain a steady input level during

conversion. The discrete time Σ-Δ ADCs also use the sample-and-

hold circuit in both the input path and the feedback loop, which

simplifies the design. Because the analog input signal is converted

to a discrete time signal by the sample-and-hold circuit, the ADCs

with the sample-and-hold circuit are also known as discrete time

ADCs.

The sample-and-hold circuit offers many benefits to the ADC de-

sign. However, some side effects of using the sample-and-hold cir-

cuit, such as charge kickback and signal aliasing, require additional

effort in designing the ADC into a system.

The CTSD modulator employs the same Σ-Δ modulation principle,

such as oversampling and noise shaping, as the discrete time

sigma-delta (DTSD) modulator, with the key difference being the

CTSD does not use the sample-and-hold circuit.

The CTSD modulator design used on the AD4134 uses both a

continuous time integrator and a continuous time DAC. This archi-

tecture offers some unique system benefits to the precision data

acquisition systems design over the discrete time ADCs.

EASY TO DRIVE INPUT AND REFERENCE

The switching action of the sample-and-hold circuit used on the

discrete time ADCs creates disturbances on the input node. There

are two main impacts of the disturbance. The first is the sudden

loading of the input node by the sampling capacitor, for which the

magnitude of the disturbance is proportional to the input differential

voltage/differential time. The second impact is from the charges

stored in the parasitic capacitance of the switches being pushed

out to the input node when the switch is closed, a phenomenon

known as charge injection or charge kickback. In either case, the

sudden change of current flow at the input of the ADC reacts with

the finite impedance of the driving circuit to create a disturbance in

the form of voltage variation. The profile of the variation depends on

the bandwidth and the impedance of the driving circuit.

To achieve the required level of accuracy, at the end of each

sampling period, the disturbed input signal must settle to the actual

source value within 1 LSB of the ADC target effective resolution,

which is particularly challenging with a higher precision or higher

input bandwidth requirement.

A common solution to overcome the input settling challenge is to

buffer the input with a high bandwidth amplifier with high output

driving capability, as shown in Figure 60.

Figure 60. Driving the Input of a Discrete Time ADC

The sample-and-hold circuit is also used by the discrete time ADC

on the reference input. A high bandwidth amplifier is also required

to drive the ADC reference input.

The drawbacks of using an ADC driving amplifier include the

following:

►

The amplifier bandwidth must be much higher than the input

signal bandwidth, leading to higher power consumption

►

The additional components in the signal chain lead to more noise

and error

►

Additional design complexity to ensure stability when driving the

dynamic capacitive load of a discrete time ADC

CTSD architecture allows the AD4134 to have a constant resistive

input characteristic. This behavior simplifies the front-end circuit

design, allowing lower bandwidth, and low power high performance

precision amplifiers to directly drive the ADC.

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