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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD4134 датащи(PDF) 40 Page - Analog Devices |
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AD4134 датащи(HTML) 40 Page - Analog Devices |
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40 / 92 page  Data Sheet AD4134 CIRCUIT INFORMATION analog.com Rev. 0 | 40 of 92 ASRC Slave Mode In slave mode, the ODR pin behaves as an input (see Figure 75). The user sets the ODR by providing a clock or pulse train at the desired ODR frequency (fODR) to the ODR pin. The AD4134 measures the ODR frequency using the input signal rising edge. An internal digital PLL tracks the ODR pin input signal frequency and uses it to set the resampling rate of the ASRC. The ADC output data is made available for sampling with respect to the ODR signal. The user must provide continuous cycles of the ODR signal until the PLL is locked by checking the STAT_PLL_LOCK bit and then reading the data. Any change in the ODR value causes the PLL to unlock and lock back again and requires a wait time before reading data. The user must also ensure that the jitter on the ODR pin is not more than 100 ns p-p to ensure that the performance is not degraded. Figure 75. ASRC Slave Mode Functional Diagram |
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