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AD4134 датащи(PDF) 11 Page - Analog Devices

номер детали AD4134
подробное описание детали  24-Bit, 4-Channel Simultaneous Sampling 1.5 MSPS Precision Alias Free ADC
PDF  92 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD4134 датащи(HTML) 11 Page - Analog Devices

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Data Sheet
AD4134
SPECIFICATIONS
analog.com
Rev. 0 | 11 of 92
Figure 2. Timing Diagram of Data Interface with Gated DCLK
Signal on DOUTx is driven out on the rising edge of DCLK. See Figure 3.
Table 4. Data Interface Timing with Free Running DCLK
Parameter
Description
Test Conditions/Comments
Min
Typ
Max
Unit
t9
ODR high time
Master mode, tDCLK > tDIGCLK
2.5 × tDCLK
3.5 × tDCLK – tDIGCLK + 4
ns
Master mode, tDCLK ≤ tDIGCLK
3 × tDIGCLK
3 × tDIGCLK + 4
ns
Slave mode, tDCLK > tDIGCLK
3 × tDCLK
ns
Slave mode, tDCLK ≤ tDIGCLK
3 × tDIGCLK
t10
ODR low time
Slave mode, tDCLK > tDIGCLK
3 × tDCLK
ns
Slave mode, tDCLK ≤ tDIGCLK
3 × tDIGCLK
t11
DCLK rising edge to ODR rising edge
Slave mode
tDCLK/2
ns
t12
ODR rising edge to DCLK rising edge
Slave mode
tDCLK/2
ns
t13
ODR sampled high to DOUTx active
3 × tDCLK
3 × tDCLK + 4
t14
DCLK rising to DOUTx invalid
Master mode
−4
ns
t15
DCLK rising to DOUTx valid
Master mode
0
2
ns
Slave mode
3
ns
t16
DCLK low time
tDCLK/2 − 1
ns
t17
DCLK high time
tDCLK/2 − 1
ns
Figure 3. Timing Diagram of Data Interface with Free Running DCLK
SDI is sampled on the rising edge of SCLK. SDO is driven out on the falling edge of SCLK. See Figure 4.



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