AD4134 datasheet(65/92 Pages) AD

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Data Sheet

AD4134

DIGITAL INTERFACE

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DATA INTERFACE

The AD4134 has a flexible data interface designed to support the

different digital host types and applications requirements.

The AD4134 can act as the data interface master or slave. The

data interface supports both gated and free running clock signals,

parallel or serial output data steaming modes, and daisy-chain

configuration.

The data interface consists of three signal types: clock, data, and

data framing signal.

Data Interface Clock

The AD4134 supports both gated and free running DCLK signals.

The ADC output data is clocked out on the DCLK rising edge.

Figure 114. DCLK Edges

DCLK is a bidirectional pin. The AD4134 can act as an interface

master and generate the DCLK signal, or act as an interface slave

and clock out data based on a received DCLK signal.

When the DCLK pin is configured as an output, the user can

choose the DCLK output frequency through the DATA_ PACK-

ET_CONFIG register or configuration of the DCLKRATEx/GPIOx

pins in pin control mode.

Refer to the Programming Output Data Rate and Clock section for

more information on how to configure the DCLK frequency.

Data Bus

The ADC output data appears on the DOUTx pins. Each AD4134

device has four data output pins: DOUT0, DOUT1, DOUT2, and

DOUT3. The user has the option to parallel output the ADC conver-

sion result on the four DOUTx pins or to serialize the data from

multiple channels and output them using one or two of the DOUTx

pins.

Parallel output configuration allows a high data rate at a low DCLK

frequency. A serialized output configuration requires fewer I/Os

from the digital host and can reduce the number of digital isolator

channels required in an isolation application. The daisy-chain mode

is available only with a serialized output configuration.

Data Framing Signal

The ODR control signal is dual purposed to act as the framing

signal for the AD4134 data interface.

The ODR pin is bidirectional with its signal direction dependent on

the ASRC mode of operation.

The output data can be driven out with respect to the ODR falling or

rising edge depending on the mode of DCLK used.

Choosing the Data Interface Mode of Operation

The direction of the ODR signal depends on the choice of the

ASRC mode of operation. See the Asynchronous Sample Rate

Converter section for more information on the ASRC.

Data Interface Status and CRC Header

The user has the option to append a byte width header to each

output data sample for additional status information and/or error

checking. The header consists of 6-bit CRC code with two status

bits, as shown in Table 36.

Table 36. Details of the Header

Bit

Bit Description

No Chip error

Filter settled and PLL locked

[5:0]

6-bit CRC

Bit 7 is cleared if an error is detected by the on-chip diagnostic

circuitry of the AD4134. See the Diagnostics section for more

details of the diagnostic features of the device.

Bit 6 is set if the digital filter on the corresponding channel is fully

settled and, when operating in ASRC slave mode, the PLL is locked

after an ODR input frequency change.

The data sample value does not reflect the correct conversion

result when Bit 6 of the header has a value of zero.

Data CRC Calculation

The CRC is calculated with the polynomial and initial seed value as

shown in Table 37.

Table 37. Data CRC Calculation

CRC Mode

Polynomial

Default Seed Value

CRC-6

x6 + x5 + x2 + x + 1

0x25

Alternative CRC Mode of Operation

The AD4134 uses a linear feedback shift register (LFSR) to calcu-

late the CRC. In pin control mode and in SPI control mode, by

default, the LFSR is reset after each data sample with the default

seed value (see Figure 115). In SPI control mode, the user has

the option to alter the LFSR resetting behavior. Configure CRC_

POLY_RST_SEL to 1 to disable the reset of the LFSR after each

sample, making the current CRC result in the seed value of the next

calculation. This mode allows the processor-based digital host to

check the CRC less frequently and still be able to detect an error in

the bit transfer.

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