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MMPF0200Z датащи(PDF) 9 Page - NXP Semiconductors |
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MMPF0200Z датащи(HTML) 9 Page - NXP Semiconductors |
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9 / 118 page ![]() Analog Integrated Circuit Device Data Freescale Semiconductor 9 PF0200Z Pin Connections Pin Definitions 48 GNDREF GND - GND Ground reference for the main band gap regulator. 49 VCORE O 3.6 V Analog Analog Core supply 50 VIN I 4.8 V Analog Main chip supply 51 VCOREDIG O 1.5 V Analog Digital Core supply 52 VCOREREF O 1.5 V Analog Main band gap reference 53 SDA I/O 3.6 V Digital I2C data line (Open drain) 54 SCL I 3.6 V Digital I2C clock 55 VDDIO I 3.6 V Analog Supply for I2C bus. Bypass with 0.1 F decoupling capacitor as close to the pin as possible. 56 PWRON I 3.6 V Digital Power On/off from processor - EP GND - GND Expose pad. Functions as ground return for buck regulators. Tie this pad to the inner and external ground planes through vias to allow effective thermal dissipation. Notes 3. 10 V Maximum voltage rating during OTP fuse programming. 7.5 V Maximum DC voltage rated otherwise. 4. Unused switching regulators should be connected as follow: Pins SWxLX and SWxFB should be unconnected and Pin SWxIN should be connected to VIN with a 0.1 F bypass capacitor. Table 2. PF0200Z Pin Definitions (continued) Pin Number Pin Name Pin Function Max Rating Type Definition |
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