MMPF0200Z datasheet(30/118 Pages) NXP

30 / 118 page

Analog Integrated Circuit Device Data



Freescale Semiconductor

PF0200Z

Functional Block Requirements and Behaviors

Power Generation

6.4.1.4

Sleep Mode

• Depending on PWRON pin configuration, Sleep mode is entered when PWRON is de-asserted and SWxOMODE bit is set.

• To exit Sleep mode, assert the PWRON pin.

In the Sleep mode, the regulator will use the set point as programmed by SW1ABOFF[5:0] for SW1A/B and by SWxOFF[6:0] for

SW2 and SW3A/B. The activated regulators will maintain settings for this mode and voltage until the next turn-on event. Table 23

shows the control bits in Sleep mode. During Sleep mode, interrupts are active and the INTB pin will report any unmasked fault

event.

6.4.1.5

Coin Cell Mode

In the Coin Cell state, the coin cell is the only valid power source (VIN = 0.0 V) to the PMIC. No turn-on event is accepted in the

Coin Cell state. Transition to the OFF state requires that VIN surpasses UVDET threshold. RESETBMCU is held low in this mode.

If the coin cell is depleted, a complete system reset will occur. At the next application of power and the detection of a Turn-on

event, the system will be re-initialized with all I2C bits including those that reset on COINPORB, are restored to their default

states.

Table 23. Regulator Mode Control

SWxOMODE

Off Operational Mode (Sleep) (34)

0Off

1PFM

Notes

34.

For sleep mode, an activated switching regulator, should use the off

mode set point as programmed by SW1ABOFF[5:0] for SW1A/B and

SWxOFF[6:0] for SW2 and SW3A/B.

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