ADE9153AACPZ datasheet(45/50 Pages) AD

45 / 50 page

Data Sheet

ADE9153A

Rev. 0 | Page 45 of 50

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x493

CONFIG3

[15:4]

Reserved

Reserved.

0x0

[3:2]

PEAK_SEL

Peak detection phase

selection.

0x0

R/W

0 Phase A and Phase B

disabled from voltage and

current peak detection.

1 Phase A Voltage and current

peak detection enabled,

Phase B current peak

detection disabled.

10 Phase A voltage and current

peak detection disabled,

Phase B current peak

detection enabled.

11 Phase A and Phase B

enabled for voltage and

current peak detection.

OIB_EN

Overcurrent detection enable

for Current Channel B.

0x0

R/W

OIA_EN

Overcurrent detection enable

for Current Channel A.

0x0

R/W

0x49A

ZX_CFG

[15:1]

Reserved

Reserved.

0x0

DISZXLPF

Zero-crossing low-pass filter

disable.

0x0

R/W

0x49D

PHSIGN

[15:8]

Reserved

Reserved.

0x0

CF2SIGN

Sign of the power in the CF2

datapath. The CF2 energy is

positive if this bit is clear

and negative if this bit is set.

0x0

CF1SIGN

Sign of the power in the CF1

datapath. See the CF2SIGN

description.

0x0

[5:2]

Reserved

Reserved.

0x0

AVARSIGN

Phase A fundamental

reactive power sign bit. The

fundamental reactive power

is positive if this bit is clear

and negative if this bit is set.

0x0

AWSIGN

Phase A active power sign

bit. The active power is

positive if this bit is clear

and negative if this bit is set.

0x0

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