ADE9153AACPZ datasheet(36/50 Pages) AD

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ADE9153A

Data Sheet

Rev. 0 | Page 36 of 50

Table 9. Register Details

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x020

CONFIG0

[31:10]

Reserved

Reserved.

0x0

Reserved

Reserved.

DISRPLPF

Set this bit to disable the

low-pass filter in the

fundamental reactive power

datapath.

0x0

R/W

DISAPLPF

Set this bit to disable the

low-pass filter in the total

active power datapath.

0x0

R/W

Reserved

Reserved.

0x0

VNOMA_EN

Set this bit to use the

nominal phase voltage rms,

VNOM, in the computation

of the Phase A total

apparent power, AVA.

0x0

RMS_OC_SRC

This bit selects the samples

used for the RMS_OC

calculation.

0x0

0 x_WAV waveforms after the

high-pass filter and phase

compensation.

1 ADC samples, before the

high-pass filter.

ZX_SRC_SEL

This bit selects whether data

going into the zero-crossing

detection circuit comes

before the high-pass filter

and phase compensation, or

afterwards.

0x0

0 After the high-pass filter and

phase compensation.

1 Before the high-pass filter

and phase compensation.

INTEN_BI

Set this bit to enable the

integrator on Current

Channel B.

0x0

R/W

RESERVED

Reserved.

0x0

R/W

HPFDIS

Set this bit to disable high-

pass filters in all current and

voltage channels.

0x0

0x023

BI_PGAGAIN

[31:0]

BI_GAIN

PGA gain for Current

Channel B.

0x0

R/W

0Gain = 1.

1Gain = 2.

10 Gain = 4.

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