ADE9153AACPZ datasheet(43/50 Pages) AD

43 / 50 page

Data Sheet

ADE9153A

Rev. 0 | Page 43 of 50

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x425

CF_LCFG

[31:21]

Reserved

Reserved.

0x0

CF2_LT

If this bit is set, the CF2 pulse

width is determined by the

CF_LTMR register value. If this

bit is equal to zero, the active

low pulse width is set as

80 ms for frequencies lower

than 6.25 Hz.

0x0

R/W

CF1_LT

If this bit is set, the CF1

pulse width is determined

by the CF_LTMR register

value. See the CF2_LT

description.

0x0

R/W

[18:0]

CF_LTMR

If the CFx_LT bit in the

CF_LCFG register is set, this

value determines the active

low pulse width of the CFx

pulse.

0x0

R/W

0x471

TEMP_TRIM

[31:16]

TEMP_OFFSET

Offset of temperature

sensor, calculated during

the manufacturing process.

0x0

[15:0]

TEMP_GAIN

Gain of temperature sensor,

calculated during the

manufacturing process.

0x0

0x481

CONFIG1

EXT_REF

Set this bit if using an

external voltage reference.

0x0

R/W

DIP_SWELL_IRQ_MODE

This bit sets the interrupt

mode for dip/swell.

0x0

R/W

0 Receive continuous

interrupts after every

DIP_CYC/SWELL_CYC cycles.

1 Receive one interrupt when

entering dip/swell condition

and another interrupt when

exiting dip/swell condition.

[13:12]

Reserved

Reserved.

0x0

BURST_EN

Set this bit to enable burst

read functionality on the

registers. Note that this bit

disables the CRC being

appended to SPI register

reads.

0x0

R/W

Reserved

Reserved.

0x0

[9:8]

PWR_SETTLE

These bits configure the

time for the power and filter-

based rms measurements to

settle before starting the

power, energy, and CF

accumulations.

0x3

R/W

0 64 ms.

1 128 ms.

10 256 ms.

11 0 ms.

[7:6]

Reserved

Reserved.

0x0

CF_ACC_CLR

Set this bit to clear the

accumulation in the digital

to frequency converter and

the CFDEN counter. This bit

automatically clears itself.

0x0

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