ADE9153AACPZ datasheet(30/50 Pages) AD

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ADE9153A

Data Sheet

Rev. 0 | Page 30 of 50

ACCESSING ON-CHIP DATA

The ADE9153A has two communication protocols for accessing

on-chip data, a fast 10 MHz SPI and a slower 4800 Baud/

115,200 Baud universal asynchronous receiver/transmitter

(UART).

After power-on or reset, to select the SPI interface, the SS pin

must be low and the SCLK pin must be high. To select the

UART interface, the SS pin must be high and the SCLK pin

must be low. When the ADE9153A is powered, the communica-

tion is set, and it is locked in until the next ADE9153A reset.

SPI PROTOCOL OVERVIEW

The ADE9153A has an SPI-compatible interface consisting of

four pins: SCLK, MOSI/RX, MISO/TX, and SS. The ADE9153A

is always an SPI slave; it never initiates a SPI communication.

The SPI interface is compatible with 16-bit and 32-bit read/write

operations. The maximum serial clock frequency supported by

this interface is 10 MHz.

The ADE9153A provides SPI burst read functionality on certain

registers, allowing multiple register to be read after sending one

command header, CMD_HDR.

3 2

ADDR[11:0]

R/W

xxx

READ = 1

WRITE = 0

DON’T CARE BITS

ADDRESS TO BE ACCESSED

Figure 55. Command Header, CMD_HDR

The ADE9153A SPI port calculates a 16-bit cyclic redundancy

check (CRC-16) of the data sent out on the MOSI/RX pin so that

the integrity of the data received by the master can be checked. The

CRC of the data sent out on the MOSI/RX pin during the last

appended to the SPI read data as part of the SPI transaction.

UART INTERFACE

The ADE9153A has a UART interface consisting of two

pins: RX and TX. This UART interface allows an isolated

communication interface to be achieved using only two low

cost opto-isolators. The UART interface is compatible with

16-bit and 32-bit read/write operations. When the UART is

selected, the Baud rate is 4800 Baud; however, a faster

communication rate of 115,200 Baud can also be selected.

The ADE9153A Baud rates are shown in Table 7.

Table 7. UART Baud Rate

Ideal Rate

(Baud)

ADE9153A Actual Rate (Baud)

(CLKIN = 12.288 MHz)

Error

4800

CLKIN/2560 = 4800

0.00%

115,200

CLKIN/104 = 118153.8

2.56%

If the UART is to be used at 4800 Baud, no action is required when

the UART interface is chosen after a reset. The 115,200 Baud rate is

chosen with a single write of 0x0052 to the UART_BAUD_

SWITCH register. The Baud rate can be switched back to

4800 Baud by writing 0x000 to the UART_BAUD_SWITCH

The UART communication is comprised of 11-bit frames with one

start bit, eight data bits, one odd parity bit, and one stop bit.

START

ODD PARITY

STOP

DATA [7:0]

Figure 56. Frame Bits

Every UART communication starts with two command frames

that contain the ADE9153A address being accessed, a read or

write bit, a bit indicating whether to include the checksum, and

then 00b as the lower two bits (see Figure 57).

42 1

R/W

00B

READ = 1

WRITE = 0

CHECKSUM

OFF = 0

ON = 1

CHIP ADDRESS

Figure 57. Command Header (CMD)

The frames are then organized with the two command header

frames, followed by the data frames, and finally an optional

checksum that is enabled in the command frames.

CMD0

CMD1

DATA0

DATA1

CHECKSUM

OPTIONAL

Figure 58. UART 16-Bit Write

CMD0

CMD1

DATA0

DATA1

CHECKSUM

OPTIONAL

Figure 59. UART 16-Bit Read

CMD0

CMD1

DATA0

DATA1

DATA2

DATA3

CHECKSUM

OPTIONAL

Figure 60. UART 32-Bit Write

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