ADE9153AACPZ datasheet(26/50 Pages) AD

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ADE9153A

Data Sheet

Rev. 0 | Page 26 of 50

Digital to Frequency Conversion—CFx Output

The ADE9153A includes two pulse outputs on the CF1 and CF2

output pins that are proportional to the energy accumulation. The

block diagram of the CFx pulse generation is shown in Figure 50.

CF2 is multiplexed with ZX and DREADY.

Calibration Frequency (CF) Energy Select

ion

The CFxSEL bits in the CFMODE register select which type of

energy to output on the CFx pins. For example, with CF1SEL =

000b and CF2SEL = 100b, CF1 indicates the total active energy,

and CF2 indicates the fundamental reactive energy.

Configuring the CFx Pulse Width

The values of the CFx_LT and the CF_LTMR bits in the

CF_LCFG register determine the pulse width.

The maximum CFx with threshold (xTHR) = 0x00100000 and

CFxDEN = 2 is 78.9 kHz. It is recommended to leave xTHR at

the default value of 0x00100000.

CFx Pulse Sign

The CFxSIGN bits in the PHSIGN register indicate whether the

energy in the most recent CFx pulse is positive or negative. The

REVPCFx bits in the status register indicate if the CFx polarity

changed sign. This feature generates an interrupt on the IRQ pin.

Clearing the CFx Accumulator

To clear the accumulation in the digital to frequency converter

and CFDEN counter, write 1 to the CF_ACC_CLR bit in the

CONFIG1 register. The CF_ACC_CLR bit automatically clears

itself.

POWER QUALITY MEASUREMENTS

Zero-Crossing Detection

The ADE9153A offers zero-crossing detection on the voltage

and both current channels. The current and voltage channel

datapaths preceding the zero-crossing detection are shown in

Figure 51 and Figure 52.

Use the ZX_SRC_SEL bit in the CONFIG0 register to select

data before the high-pass filter or after phase compensation to

configure the inputs to zero-crossing detection. ZX_SRC_SEL =

0 by default after reset.

To provide protection from noise, voltage channel zero-crossing

events (ZXAV) do not generate if the absolute value of the LPF1

output voltage is smaller than the threshold, ZXTHRSH. The

current channel zero-crossing detection outputs, ZXAI and

ZXBI, are active for all input signals levels.

Calculate the zero-crossing threshold, ZXTHRSH, from the

following equation:

ZXTHRSH =

)

(

)

(



Attenuatio

LPF1

Scale

Full

WAV

where

V_WAV at Full Scale is ±37,282,702 decimal.

LPF1 Attenuation is 0.86 at 50 Hz, and 0.81 at 60 Hz.

x is the dynamic range below which the voltage channel zero

crossing must be blocked.

HPF

ZERO-CROSSING

DETECTION

LPF1

AVGAIN

PHASE

COMP

HPFDIS

ZX_SRC_SEL

AV_WAV

÷32

Figure 51. Voltage Channel Signal Path Preceding Zero-Crossing Detection

xIGAIN

HPF

PHASE

COMP

INTEGRATOR

HPFDIS

INTEN_BI

xI_WAV

ZX_SRC_SEL

ZX DETECTION

LPF1

÷32

Figure 52. Current Channel Signal Path Preceding Zero-Crossing Detection

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