ADSP-SC591 datasheet(27/143 Pages) AD

27 / 143 page

Rev. PrD

Page 27 of 143

May 2021

ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594

Preliminary Technical Data

DMC_VREF[n]

Input

Voltage Reference. Connects to half of the VDD_DMC voltage.

DMC_WE

Output

Write Enable. Defines the operation for external dynamic memory to perform in conjunction with

other DMC command signals. Connect to the WE input of dynamic memory.

ETH_COL

Input

MII Collision Detect. Collision detect input signal valid only in MII.

ETH_CRS

Input

MII Carrier Sense. Asserted by the PHY when either the transmit or receive medium is not idle.

Deasserted when both are idle. This signal is not used in RMII/RGMII modes.

ETH_MDC

Output

Management Channel Clock. Clocks the MDC input of the PHY for RMII/RGMII.

ETH_MDIO

InOut

Management Channel Serial Data. Bidirectional data bus for PHY control for RMII/RGMII.

ETH_PTPAUXIN[n]

Input

PTP Auxiliary Trigger Input. Assert this signal to take an auxiliary snapshot of the time and store it

in the auxiliary time stamp FIFO.

ETH_PTPCLKIN[n]

Input

PTP Clock Input. Optional external PTP clock input.

ETH_PTPPPS[n]

Output

PTP Pulse Per Second Output. When the advanced time stamp feature enables, this signal is asserted

based on the PPS mode selected. Otherwise, this signal is asserted every time the seconds counter is

incremented.

ETH_REFCLK

Input

Reference Clock. Externally supplied Ethernet clock.

ETH_RXCLK_REFCLK

Input

RXCLK (10/100/1000) or REFCLK (10/100).

ETH_RXCTL_CRSRX_DV InOut

RXCTL (10/100/1000) or CRSRX_DV (10/100). In RGMII mode, RXCTL multiplexes receive data valid

and receiver error. In RMII mode, CRSRX_DV is carrier sense and receive data valid (CRS_DV), multi-

plexed on alternating clock cycles. In MII mode, CRSRX_DV is receive data valid (RX_DV), asserted by

the PHY when the data on ETH_RXD[n] is valid.

ETH_RXD[n]

Input

Receive Data n. Receive data bus.

ETH_RXERR

Input

Receive Error.

ETH_TXCLK

Input

Reference Clock. Externally supplied Ethernet clock.

ETH_TXCTL_TXEN

Output

TXCTL (10/100/1000) or TXEN (10/100).

ETH_TXD[n]

Output

Transmit Data n. Transmit data bus.

ETH_TXEN

Output

Transmit Enable. When asserted, this signal indicates the data on ETH_TXD[n] is valid.

HADC_EOC_DOUT

Output

End of Conversion/Serial Data Out. Transitions high for one cycle of the HADC internal clock at the

end of every conversion. Alternatively, HADC serial data out can be seen by setting the appropriate

bit in HADC_CTL.

HADC_MUX[n]

Output

Controls to External Multiplexer. Allows additional input channels when connected to an external

multiplexer.

HADC_VIN[n]

Input

Analog Input at Channel n. Analog voltage inputs for digital conversion.

HADC_VREFN

Input

Ground Reference for ADC. Connect to an external voltage reference that meets data sheet

specifications.

HADC_VREFP

Input

External Reference for ADC. Connect to an external voltage reference that meets data sheet

specifications.

JTG_TCK

Input

JTAG Clock. JTAG test access port clock.

JTG_TDI

Input

JTAG Serial Data In. JTAG test access port data input.

JTG_TDO

Output

JTAG Serial Data Out. JTAG test access port data output.

JTG_TMS

Input

JTAG Mode Select. JTAG test access port mode select.

JTG_TRST

Input

JTAG Reset. JTAG test access port reset.

LP_ACK

InOut

Acknowledge. Provides handshaking. When the link port is configured as a receiver, ACK is an output.

When the link port is configured as a transmitter, ACK is an input.

LP_CLK

InOut

Clock. When the link port is configured as a receiver, CLK is an input. When the link port is configured

as a transmitter, CLK is an output.

LP_D[n]

InOut

Data n Data bus. Input when receiving, output when transmitting.

MLB_CLK

Input

Single Ended Clock.

MLB_CLKN

Input

Differential Clock (–).

MLB_CLKOUT

Output

Single Ended Clock Out.

Table 9. ADSP-2159x/ADSP-SC59x Detailed Signal Descriptions (Continued)

Signal Name

Direction

Description

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