ADSP-SC591 datasheet(21/143 Pages) AD

21 / 143 page

Rev. PrD

Page 21 of 143

May 2021

ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594

Preliminary Technical Data

General-Purpose I/O (GPIO)

Each general-purpose port pin can be individually controlled by

manipulating the port control, status, and interrupt registers:

• The GPIO direction control register specifies the direction

of each individual GPIO pin as input or output.

• GPIO control and status registers have a write-one-to-

modify mechanism that allows any combination of individ-

ual GPIO pins to be modified in a single instruction,

without affecting the level of any other GPIO pins.

• GPIO interrupt mask registers allow each individual GPIO

pin to function as an interrupt to the processors. GPIO pins

defined as inputs can be configured to generate hardware

interrupts, whereas output pins can be triggered by soft-

ware interrupts.

• GPIO interrupt sensitivity registers specify whether indi-

vidual pins are level or edge sensitive and specify, if edge

sensitive, whether the rising edge or both the rising and

falling edges of the signal are significant.

Pin Interrupts

Every port pin on the processors can request interrupts in either

an edge sensitive or a level sensitive manner with programmable

polarity. Interrupt functionality is decoupled from GPIO opera-

tion. Eight system level interrupt channels (PINT0–PINT7) are

reserved for this purpose. Each of these interrupt channels can

manage up to 32 interrupt pins. The assignment from pin to

interrupt is not performed on a pin by pin basis. Rather, groups

of eight pins (half ports) are flexibly assigned to interrupt

channels.

Every pin interrupt channel features a special set of 32-bit mem-

ory-mapped registers that enable half port assignment and

interrupt management. This functionality includes masking,

identification, and clearing of requests. These registers also

enable access to the respective pin states and use of the interrupt

latches, regardless of whether the interrupt is masked. Most

control registers feature multiple MMR address entries to write

one to set or write one to clear them individually.

Core Flags I/O Pins

The processor features 32 flag I/O pins (16 per SHARC+ core),

which allow for external control and monitoring of the

SHARC+ core FLAGS register. User code can write to bits in

this register to be driven to pins configured as outputs, and code

execution can be made conditional based on the settings of the

pins configured as inputs.

SYSTEM ACCELERATION

The following sections describe the system acceleration blocks

of the ADSP-2159x/ADSP-SC59x processors.

Finite Impulse Response (FIR) Accelerator

The finite impulse response (FIR) accelerator consists of a

1024 word coefficient memory, a 1024 word deep delay line for

the data, and four multiplier-accumulator (MAC) units. A con-

troller manages the accelerator. The FIR accelerator runs at the

SHARC core clock frequency. The FIR accelerator can access all

memory spaces and can run concurrently with the other accel-

erators on the processor.

Infinite Impulse Response (IIR) Accelerator

The infinite impulse response (IIR) accelerator consists of a

1440 word coefficient memory for storage of biquad coeffi-

cients, a data memory for storing the intermediate data, and one

MAC unit. A controller manages the accelerator. The IIR

accelerator runs at the SHARC core clock frequency. The IIR

accelerator can access all memory spaces and run concurrently

with the other accelerators on the processor.

Note: There are four IIR accelerators per SHARC core.

SYSTEM DESIGN

The following sections provide an introduction to system design

features and power supply issues.

Clock Management

The processors provide three operating modes, each with a dif-

ferent performance and power profile. Control of clocking to

each of the processor peripherals reduces power consumption.

The processors do not support any low power operation modes.

Control of clocking to each of the processor peripherals can

reduce the power consumption.

Reset Control Unit (RCU)

Reset is the initial state of the whole processor, or the core, and

is the result of a hardware or software triggered event. In this

state, all control registers are set to default values and functional

units are idle. Exiting a full system reset begins with the core

ready to boot.

The reset control unit (RCU) controls how all the functional

units enter and exit reset. Differences in functional require-

ments and clocking constraints define how reset signals are

generated. Programs must guarantee that none of the reset

functions put the system into an undefined state or cause

resources to stall. This requirement is particularly important

when the core resets (programs must ensure that there is no

pending system activity involving the core when it is reset).

From a system perspective, reset is defined by both the reset tar-

get and the reset source.

The reset target is defined as the following:

• System reset—all functional units except the RCU are set to

default states.

• Hardware reset—all functional units are set to default states

without exception. History is lost.

• Core only reset—affects the core only. When in reset state,

the core is not accessed by any bus requester.

The reset source is defined as the following:

• System reset—can be triggered by software (writing to the

RCU_CTL register) or by another functional unit, such as

the dynamic power management (DPM) unit or any of the

SEC, TRU, or emulator inputs.

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