ADSP-SC591 datasheet(5/143 Pages) AD

5 / 143 page

Rev. PrD

Page 5 of 143

May 2021

ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594

Preliminary Technical Data

Table 1. Processor Features1

Processor Feature

ADSP-21591

ADSP-21593

ADSP-21594

ADSP-SC591

ADSP-SC592

ADSP-SC594

Arm Cortex-A5 (MHz, Maximum)2

N/A

600, 800

1000

800, 1000

Arm Core L1 Cache (I, D kB)

32, 32

Arm Core L2 Cache (kB)

256

SHARC+ Core1 (MHz, Maximum)2

800

800, 1000

600, 800

1000

800, 1000

SHARC+ Core2 (MHz, Maximum)2

N/A

SHARC L1 SRAM (kB)

2 × 640

1 × 640

2 × 640

System Memory

L2 SRAM (Shared) (MB)

DDR3/DDR3L Controller (16-Bit)

Hardware Accelerators

FIRs Per SHARC+ Core

IIRs Per SHARC+ Core

Security Cryptographic Engine

Yes

DAI (Includes SRU and DRU)

Full SPORTs

8 (4 per DAI)

S/PDIF Receive/Transmit

2 (1 per DAI)

ASRCs

8 (4 per DAI)

PCGs

8 (4 per DAI)

4-Channel PDM MIC Input

2 (1 per DAI)

Pin Buffers

28 (14 per DAI)

40 (20 per DAI)

Multiplexed Peripherals

MLB 3-Pin

Yes3

Link Ports

GP Counter

I2C (TWI)

Watchdog Timers

GP Timers

164

Octal SPI

Quad-Data Bit SPI

Dual-Data Bit SPI

UARTs

ePPI

N/A

USB 2.0 HS OTG Controller

N/A

EMAC Std

10/100

EMAC Std/AVB + Timer IEEE 1588

10/100/1000

CAN FD

MLB 6-Pin

N/A

Yes3

Multichannel 12-Bit ADC

4-channel

8-channel5

GPIO Ports

Port A to Port C

Port A to Port I

GPIO + DAI Pins

40 + 28

135 + 40

Package Options

400- ball BGA_ED

ADSP-2156x Pin-Compatible

Yes6

1 N/A means not applicable.

2 Multiple values indicate various speed grades. See Planned Production Products.

3 Applies to automotive models only. See Planned Automotive Production Products.

4 For the ADSP-21591 and ADSP-21593 models, GP timer instances TIMER10-TIMER15 are not brought out to package pins and must only be configured for internal modes

of operation.

5 The HADC can support up to 7 additional channels using an external multiplexer.

6 Pin compatible with the ADSP-21566, ADSP-21567, and ADSP-21569.

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