ADSP-SC591 datasheet(13/143 Pages) AD

13 / 143 page

Rev. PrD

Page 13 of 143

May 2021

ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594

Preliminary Technical Data

System Crossbars (SCBs)

The system crossbars (SCBs) are the fundamental building

blocks of a switch fabric style for on-chip system bus intercon-

nection. The SCBs connect system bus requesters to system bus

completers, providing concurrent data transfer between multi-

ple bus requesters and multiple bus completers. A hierarchical

model—built from multiple SCBs—provides a power and area

efficient system interconnection.

The SCBs provide the following features:

• Highly efficient, pipelined bus transfer protocol for sus-

tained throughput

• Full-duplex bus operation for flexibility and reduced

latency

• Concurrent bus transfer support to allow multiple bus

requesters to access bus completers simultaneously

• Protection model (privileged/secure) support for selective

bus interconnect protection

Direct Memory Access (DMA)

The processors use direct memory access (DMA) to transfer

data within memory spaces or between a memory space and a

peripheral. The processors can specify data transfer operations

and return to normal processing while the fully integrated DMA

controller carries out the data transfers independent of proces-

sor activity.

DMA transfers can occur between memory and a peripheral or

between one memory and another memory. Each memory to

memory DMA stream uses two channels: the source channel

and the destination channel.

All DMA channels can transport data to and from all on-chip

and off-chip memories. Programs can use two types of DMA

transfers: descriptor-based or register-based. Register-based

DMA allows the processors to program DMA control registers

directly to initiate a DMA transfer. On completion, the DMA

control registers automatically update with original setup values

for continuous transfer. Descriptor-based DMA transfers

require a set of parameters stored within memory to initiate a

DMA sequence. Descriptor-based DMA transfers allow

multiple DMA sequences to be chained together. Program a

DMA channel to set up and start another DMA transfer auto-

matically after the current sequence completes.

The DMA engine supports the following DMA operations:

• A single linear buffer that stops on completion

• A linear buffer with negative, positive, or zero stride length

Table 5. Memory Map of Mapped I/Os1

Byte Address Space

Arm Cortex-A5:

Data Access and

Instruction Fetch

SHARC+: Data Access

Normal Word Address Space

SHARC+ Data Access

VISA Address Space

SHARC+ Instruction Fetch

ISA Address Space

SHARC+ Instruction Fetch

SPI2/OSPI0 Memory

(512 MB)2

0x60000000–0x600FFFFF

0x04000000–0x07FFFFFF

0x00F80000–0x00FFFFFF

0x00780000–0x007AAAAA

0x60100000–0x602FFFFF

Not available

0x007AAAAB–0x007FFFFF

0x60300000–0x603FFFFF

0x00E80000–0x00EFFFFF

0x00680000–0x006AAAAA

0x60400000–0x605FFFFF

Not available

0x006AAAAB–0x006FFFFF

0x60600000–0x6FFFFFFF

Not available

0x70000000–0x7FFFFFFF

Not available

1 The Arm Cortex-A5 can access the entire byte address space. The SHARC+ VISA/ISA address space for instruction fetch and the normal word address space for data access

do not cover the entire byte address space.

2 For the ADSP-SC592/SC594/21594 processors, the SPI2/OSPI0 memory-mapped I/O space can be configured to be shared between the OSPI0 and SPI2 peripherals using

the REG_SCB5_REMAP.REMAP field. See the ADSP-2159x/ADSP-SC591/592/594 SHARC+ Processor Hardware Reference for details.

Table 6. DMC Memory Map1

Byte Address Space

Arm Cortex-A5: Data Access

and Instruction Fetch

SHARC+: Data Access

Normal Word Address Space

SHARC+ Data Access

VISA Address Space

SHARC+ Instruction Fetch

ISA Address Space

SHARC+ Instruction Fetch

DMC0 (1 GB)

0x80000000–0x805FFFFF

0x10000000–0x17FFFFFF

Not applicable

0x00400000–0x004FFFFF

0x80600000–0x809FFFFF

Not applicable

0x80A00000–0x80FFFFFF

0x00800000–0x00AFFFFF

Not applicable

0x81000000–0x9FFFFFFF

Not applicable

0xA0000000–0xBFFFFFFF

Not applicable

1 The Arm Cortex-A5 can access the entire byte address space. The SHARC+ VISA/ISA address space for instruction fetch and the normal word address space for data access

do not cover the entire byte address space.

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