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CDCE706 датащи(PDF) 28 Page - Texas Instruments

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номер детали CDCE706
подробное описание детали  PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER
PDF  32 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI - Texas Instruments

CDCE706 датащи(HTML) 28 Page - Texas Instruments

Back Button CDCE706 Datasheet HTML 24Page - Texas Instruments CDCE706 Datasheet HTML 25Page - Texas Instruments CDCE706 Datasheet HTML 26Page - Texas Instruments CDCE706 Datasheet HTML 27Page - Texas Instruments CDCE706 Datasheet HTML 28Page - Texas Instruments CDCE706 Datasheet HTML 29Page - Texas Instruments CDCE706 Datasheet HTML 30Page - Texas Instruments CDCE706 Datasheet HTML 31Page - Texas Instruments CDCE706 Datasheet HTML 32Page - Texas Instruments  
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Cycle
Cross Coupling, Spur Suppression and Noise Rejection
CDCE706
SCAS815A – OCTOBER 2005 – REVISED OCTOBER 2005
controlled edge with respect to a t(
Θ) mean in a random sample of cycles. Phase jitter, Time Interval Error (TIE),
or Wander are used in literature to describe long-term variation in frequency. As of ITU-T: G.810, wander is
defined as phase variation at rates less than 10 Hz while jitter is defined as phase variation greater than 10 Hz.
The measurement interval must be long enough to gain a meaningful result. Wander can be caused by
temperature drift, aging, supply voltage drift, etc.
Figure 23. Snapshot of Phase Jitter
Cross-Coupling in ICs occurs through interactions between several parts of the chip such as between output
stages, metal lines, bond wires, substrate, etc. The coupling can be capacitive, inductive and resistive (ohmic)
induced by output switching, leakage current, ground bouncing, power supply transients, etc.
The CDCE706 is designed in BiCMOS process technology incorporating silicon-germanium (SiGe) technology.
This process gives excellent performance in linearity, low power consumption, best-in-class noise performance
and very good isolation characteristic between the on-chip components.
The good isolation was a major criteria to use BiCMOS process as it minimizes the coupling effect. Even if all
three PLLs are active and all outputs are on, the noise suppression is clearly above 50 dB. Figure 24 and
Figure 25 show an example of noise coupling, spur-suppression, and power supply noise rejection of CDCE706.
Die respective measurement conditions are shown in Figure 24 and Figure 25.
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