www.ti.com

−40

−30

−20

−10

0

10

20

30

40

1

1001

2001

3001

4001

5001

6001

7001

8001

9001

10001

Cycle

−25

−20

−15

−10

−5

0

5

10

15

20

25

1

1001

2001

3001

4001

5001

6001

7001

8001

9001

10001

Cycle

CDCE706

SCAS815A – OCTOBER 2005 – REVISED OCTOBER 2005

Figure 21. Snapshot of Cycle-to-Cycle Jitter

random sample of cycles. In reference to a PLL, period jitter is the worst-case period deviation from the ideal that

would ever occur on the PLLs outputs. This is also referred to as short-term jitter.

Figure 22. Snapshot of Period Jitter

27