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CDCE706

SCAS815A – OCTOBER 2005 – REVISED OCTOBER 2005

IS1

IS0

Function

0

0

CLK_IN0 is Crystal Oscillator Input and CLK_IN1 is serving as Crystal Oscillator Output.

Yes

CLK_IN0 and CLK_IN1 are two LVCMOS Inputs. CLK_IN0 or CLK_IN1 are selectable via

0

1

CLK_SEL control pin.

1

0

CLK_IN0 and CLK_IN1 serve as differential signal inputs.

1

1

Reserved

(1)

In case the crystal input or differential clock input is selected, the input clock selection, Byte 10, Bit [4], is not relevant.

(2)

Unless customer specific setting.

Byte 12, Bit [6]: Power-Down Mode (except SMBus)

PD

Power-Down Mode

0

Normal Device Operation

Yes

1

(1)

Unless customer specific setting.

(2)

In power down, all PLLs and the Clock-Input-Stage are going into power-down mode, all outputs are in 3-State, all actual register

settings will be maintained and SMBus stays active. Power-Down Mode overwrites 3-State or Low-State of S0 and S1 setting in Byte 10.

Byte 13 to 18, Bit [6:0]: Outputs Switch Matrix - 6x7-Bit Divider P0-P5

DIVYx6

DIVYx5

DIVYx4

DIVYx3

DIVYx2

DIVYx1

DIVYx0

Div by

0

0

0

0

0

0

0

Not allowed

0

0

0

0

0

0

1

1

0

0

0

0

0

1

0

2

•

•

•

1

1

1

1

1

0

1

125

1

1

1

1

1

1

0

126

1

1

1

1

1

1

1

127

(1)

Unless customer specific setting.

(2)

Default setting of divider P0 = 1, P1 = 4, P2 = 2, P3 = 2, P4 = 5, and P5 = 1

Byte 19 to 24, Bit [5:4]: LVCMOS Output Rise/Fall Time Setting at Y0-Y5

SRCYx1

SRCYx0

Yx

0

0

0

1

1

0

Yes

1

1

(1)

Unless customer specific setting.

Byte 19 to 24, Bit [2:0]: Outputs Switch Matrix (6 x 6 Switch B) Divider (P0-P5) Selection for Outputs Y0-Y5

SWBYx2

SWBYx1

SWBYx0

Any Output Yx

0

0

0

Divider P0

Y0

0

0

1

Divider P1

Y1

0

1

0

Divider P2

Y2

0

1

1

Divider P3

Y3

1

0

0

Divider P4

Y4

1

0

1

Divider P5

Y5

1

1

0

Reserved

1

1

1

Reserved

(1)

Unless customer specific setting.

16